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[ARM] Fix PR 40153


I'm not entirely sure if this was a latent bug or not, but it's
certainly become more obvious in the last few weeks, causing major
failures in C++ tests (probably as a result of Paulo's recent changes).

The pattern for cstoresi_nltu_thumb1 was incorrectly expanding to an RTL
expression containing GTU, rather than the intended LTU.  Even though,
ultimately the pattern emitted the correct assembly code this permits
the optimizers to make incorrect assumptions.

Fixed thusly:

2009-05-16  Richard Earnshaw  <rearnsha@arm.com>

	PR target/40153
	* arm.md (cstoresi_nltu_thumb1): Use a neg of ltu as the pattern name
	implies.


*** gcc/config/arm/arm.md	(revision 147649)
--- gcc/config/arm/arm.md	(local)
*************** (define_insn "*cstoresi_ne0_thumb1_insn"
*** 7977,7983 ****
  
  (define_insn "cstoresi_nltu_thumb1"
    [(set (match_operand:SI 0 "s_register_operand" "=l,l")
!         (neg:SI (gtu:SI (match_operand:SI 1 "s_register_operand" "l,*h")
  			(match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r"))))]
    "TARGET_THUMB1"
    "cmp\\t%1, %2\;sbc\\t%0, %0, %0"
--- 7977,7983 ----
  
  (define_insn "cstoresi_nltu_thumb1"
    [(set (match_operand:SI 0 "s_register_operand" "=l,l")
!         (neg:SI (ltu:SI (match_operand:SI 1 "s_register_operand" "l,*h")
  			(match_operand:SI 2 "thumb1_cmp_operand" "lI*h,*r"))))]
    "TARGET_THUMB1"
    "cmp\\t%1, %2\;sbc\\t%0, %0, %0"

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