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Add fp_type for powerpc-xilinx-eabi FP templates


The attached patch adds missing fp_type attributes to FP
templates, used by Xilinx FPU pipeline scheduler.

--
Michael Eager	 eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306  650-325-8077
2009-05-08  Michael Eager <eager@eagercon.com>

	* config/rs6000/rs6000.md (subsf3, mulsf3, anonymous patterns): Add
	fp_type.
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/rs6000.md gcc/gcc/config/rs6000/rs6000.md
--- gcc-orig/gcc/config/rs6000/rs6000.md	2009-05-07 17:44:27.000000000 -0700
+++ gcc/gcc/config/rs6000/rs6000.md	2009-05-07 18:03:31.000000000 -0700
@@ -5209,7 +5209,8 @@
 		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
   "{fa|fadd} %0,%1,%2"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "fp_type" "fp_addsub_d")])
 
 (define_expand "subsf3"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -5233,7 +5234,8 @@
 		  (match_operand:SF 2 "gpc_reg_operand" "f")))]
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
   "{fs|fsub} %0,%1,%2"
-  [(set_attr "type" "fp")])
+  [(set_attr "type" "fp")
+   (set_attr "fp_type" "fp_addsub_d")])
 
 (define_expand "mulsf3"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -5257,7 +5259,8 @@
 		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS"
   "{fm|fmul} %0,%1,%2"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "fp_type" "fp_mul_d")])
 
 (define_expand "divsf3"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")
@@ -5321,7 +5324,8 @@
 		 (match_operand:SF 3 "gpc_reg_operand" "f")))]
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
   "{fma|fmadd} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "fp_type" "fp_maddsub_s")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
@@ -5341,7 +5345,8 @@
 		  (match_operand:SF 3 "gpc_reg_operand" "f")))]
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
   "{fms|fmsub} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "fp_type" "fp_maddsub_d")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
@@ -5372,7 +5377,8 @@
 			 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
   "{fnma|fnmadd} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "fp_type" "fp_maddsub_d")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
@@ -5382,7 +5388,8 @@
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
    && ! HONOR_SIGNED_ZEROS (SFmode)"
   "{fnma|fnmadd} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "fp_type" "fp_maddsub_d")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
@@ -5413,7 +5420,8 @@
 			  (match_operand:SF 3 "gpc_reg_operand" "f"))))]
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD"
   "{fnms|fnmsub} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "fp_type" "fp_maddsub_d")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
@@ -5423,7 +5431,8 @@
   "! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
    && ! HONOR_SIGNED_ZEROS (SFmode)"
   "{fnms|fnmsub} %0,%1,%2,%3"
-  [(set_attr "type" "dmul")])
+  [(set_attr "type" "dmul")
+   (set_attr "fp_type" "fp_maddsub_d")])
 
 (define_expand "sqrtsf2"
   [(set (match_operand:SF 0 "gpc_reg_operand" "")

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