This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [RFC] Run fast RTL DCE pass at -O0

> > Is running SSA DCE maybe cheaper?
> I think this would break debugging, it's much more aggressive.  But I'll give 
> it a whirl and see what happens.
> > Doesn't this affect the ability to debug? 
> No, it doesn't, only pseudos are DCEd like with flow.c.
> > NOPs?
> Yes, special NOPs inserted at -O0, they are quite rare.

We used to run RTL DCE for some time after DF branch merge.  It was
causing regressions on GDB testsuite.
I think we can do it but we need

 1) mark all sets to user vars to be live. On RTL all vars live in
 memory as far as I can remember, so it will in general work, but we
 need to care vars declared to registers via asm extension.
 On SSA this should be easy to test.
 2) Avoid removing last instruction that has different non-0 locator from its first
 predecestor or sucesstor with non-0 locator in same BB, so
 breakpointing on given line number does not change behaviour. 
 If DCE notices removing such instruction, it can probably turn it into
 NOP. This should catch all cases of NOPs already being in code for good
 reason so we should not need special handling of these as done in the
 proposed patch.

As also mentioned in other thread, other candidate for -O0 would be
nothrow discovery. It saves a lot of code in C++ and does not affect
debug info since it only makes CFG more precise.

> -- 
> Eric Botcazou

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]