This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[cond-optab] final tweaks part 1


With only a handful of targets still running the assembly language
comparison (m68k, alpha, pa, sh64, avr, pdp11, score), here are the
fixes exposed by the test run on the other targets.

Here are the most interesting changes:

compare-arm.log 1 file changed, 547 insertions(+), 665 deletions(-)
compare-bfin.log 1 file changed, 32533 insertions(+), 56395 deletions(-)
compare-m32c.log 1 file changed, 676 insertions(+), 1234 deletions(-)
compare-sparc.log 1 file changed, 432 insertions(+), 2552 deletions(-)

while here are the negative ones (PRs have been filed for this and other):

- compare-mn10300.log 1 file changed, 8817 insertions(+), 8292 deletions(-)
most pessimizations are at -O1 and disappear at -O2.

- m68k is fine except for ColdFire (PR39726).

MIPS has a handful of quite pessimized tests (PR39725), but except those
it's neutral leaning towards better.

Maintainers that wish to look at the log files can contact me.

Paolo
2009-04-10  Paolo Bonzini  <bonzini@gnu.org>

	* config/bfin/bfin.md (cbranchsi4): Remove BImode from operand 0.
	(cstorebi4): Do not expand NE.
	(movbisi): Duplicate insn, split it to zero_extend.
	* config/mmix/mmix.md (movdfcc): Do not handle LE and GE.
	* config/cris/cris.c (cris_normal_notice_update_cc): Handle btstq
	on one bit.
	* config/crx/crx.md (cc_reg_operand): New.
	(any_cond): Delete.
	(cbranchcc4): New.
	(cbranch<mode>4): Use ordered_comparison_operator.
	* config/m32c/cond.md (movqicc_eq_<mode>): Undo change.
	(movhicc_eq_<mode>): Undo change.
	* config/m32c/m32c.md (eqne_cond): Undo.
	* config/sh/sh.md (cstoresi4): Use cmpsi_operand to allow set from T.
	(cstoresi4, cstoredi4): Fix pasto.
	* config/m68hc11/m68hc11 (m68hc11_notice_update_cc): Look into
	a compare with 0.
	
	* final.c (final_scan_insn): Look into compare with 0, but also check
	if cc_status.value is the full compare.

Index: gcc/config/bfin/bfin.md
===================================================================
--- gcc/config/bfin/bfin.md	(branch cond-optab)
+++ gcc/config/bfin/bfin.md	(working copy)
@@ -2367,7 +2367,7 @@
 
 (define_expand "cbranchsi4"
   [(set (pc)
-        (if_then_else (match_operator:BI 0 "ordered_comparison_operator"
+        (if_then_else (match_operator 0 "ordered_comparison_operator"
                        [(match_operand:SI 1 "register_operand" "")
                         (match_operand:SI 2 "reg_or_const_int_operand" "")])
                    (label_ref (match_operand 3 "" ""))
@@ -2442,11 +2442,11 @@
        (ne:SI (match_dup 4) (const_int 0)))]
   ""
 {
+  /* It could be expanded as a movbisi instruction, but the portable
+     alternative produces better code.  */
   if (GET_CODE (operands[1]) == NE)
-    {
-      emit_insn (gen_movbisi (operands[0], operands[2]));
-      DONE;
-    }
+    FAIL;
+
   operands[4] = bfin_cc_rtx;
 })
 
@@ -2502,13 +2502,16 @@
   "CC = %1;"
   [(set_attr "length" "2")])
 
-(define_insn "movbisi"
+(define_insn_and_split "movbisi"
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ne:SI (match_operand:BI 1 "register_operand" "C")
 	       (const_int 0)))]
   ""
-  "%0 = CC;"
-  [(set_attr "length" "2")])
+  "#"
+  ""
+  [(set (match_operand:SI 0 "register_operand" "")
+	(zero_extend:SI (match_operand:BI 1 "register_operand" "")))]
+  "")
 
 (define_insn "notbi"
   [(set (match_operand:BI 0 "register_operand" "=C")
Index: gcc/config/mmix/mmix.md
===================================================================
--- gcc/config/mmix/mmix.md	(branch cond-optab)
+++ gcc/config/mmix/mmix.md	(working copy)
@@ -710,6 +710,9 @@ DIVU %1,%1,%2\;GET %0,:rR\;NEGU %2,0,%0\
   "
 {
   enum rtx_code code = GET_CODE (operands[1]);
+  if (code == LE || code == GE)
+    FAIL;
+
   operands[4] = mmix_gen_compare_reg (code, XEXP (operands[1], 0),
 				      XEXP (operands[1], 1));
   operands[5] = gen_rtx_COMPARE (GET_MODE (operands[4]),
Index: gcc/config/cris/cris.c
===================================================================
--- gcc/config/cris/cris.c	(branch cond-optab)
+++ gcc/config/cris/cris.c	(working copy)
@@ -1438,7 +1438,9 @@ cris_normal_notice_update_cc (rtx exp, r
 	  else
 	    cc_status.value1 = SET_SRC (exp);
 
-	  if (GET_CODE (cc_status.value1) == ZERO_EXTRACT)
+          /* Handle flags for the special btstq on one bit.  */
+	  if (GET_CODE (cc_status.value1) == ZERO_EXTRACT
+	      && XEXP (cc_status.value1, 1) == const1_rtx)
 	    {
 	      if (CONST_INT_P (XEXP (cc_status.value1, 0)))
 		/* Using cmpq.  */
Index: gcc/config/crx/crx.md
===================================================================
--- gcc/config/crx/crx.md	(branch cond-optab)
+++ gcc/config/crx/crx.md	(working copy)
@@ -63,6 +63,10 @@
   (ior (match_code "symbol_ref")
        (match_operand 0 "register_operand")))
 
+(define_predicate "cc_reg_operand"
+  (and (match_code "reg")
+       (match_test "REGNO (op) == CC_REGNUM")))
+
 (define_predicate "nosp_reg_operand"
   (and (match_operand 0 "register_operand")
        (match_test "REGNO (op) != SP_REGNUM")))
@@ -107,8 +111,6 @@
 (define_code_iterator mima_oprnd [smax umax smin umin])
 (define_code_attr mimaIsa [(smax "maxs") (umax "maxu") (smin "mins") (umin "minu")])
 
-(define_code_iterator any_cond [eq ne gt gtu lt ltu ge geu le leu])
-
 ;;  Addition Instructions
 
 (define_insn "adddi3"
@@ -522,9 +524,21 @@
 
 ;;  Compare and Branch Instructions
 
+(define_insn "cbranchcc4"
+  [(set (pc)
+       (if_then_else (match_operator 0 "ordered_comparison_operator"
+		       [(match_operand:CC 1 "cc_reg_operand" "r")
+			(match_operand 2 "cst4_operand" "L")])
+                     (label_ref (match_operand 3 ""))
+                     (pc)))]
+  ""
+  "b%d0\t%l3"
+  [(set_attr "length" "6")]
+)
+
 (define_insn "cbranch<mode>4"
   [(set (pc)
-	(if_then_else (match_operator 0 "comparison_operator"
+	(if_then_else (match_operator 0 "ordered_comparison_operator"
 			[(match_operand:CRXIM 1 "register_operand" "r")
 			 (match_operand:CRXIM 2 "reg_or_cst4_operand" "rL")])
 		      (label_ref (match_operand 3 "" ""))
Index: gcc/config/m32c/cond.md
===================================================================
--- gcc/config/m32c/cond.md	(branch cond-optab)
+++ gcc/config/m32c/cond.md	(working copy)
@@ -186,10 +186,10 @@
   [(set_attr "flags" "x")]
 )
 
-(define_insn_and_split "movqicc_eq_<mode>"
+(define_insn_and_split "movqicc_<code>_<mode>"
   [(set (match_operand:QI 0 "register_operand" "=R0w")
-        (if_then_else:QI (eq:QI (match_operand:QHPSI 1 "mra_operand" "RraSd")
-				(match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
+        (if_then_else:QI (eqne_cond:QI (match_operand:QHPSI 1 "mra_operand" "RraSd")
+				       (match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
 			  (match_operand:QI 3 "const_int_operand" "")
 			  (match_operand:QI 4 "const_int_operand" "")))]
   ""
@@ -199,17 +199,17 @@
 	(compare (match_dup 1)
 		 (match_dup 2)))
    (set (match_dup 0)
-        (if_then_else:QI (eq:QI (reg:CC FLG_REGNO) (const_int 0))
+        (if_then_else:QI (eqne_cond:QI (reg:CC FLG_REGNO) (const_int 0))
 			 (match_dup 3)
 			 (match_dup 4)))]
   ""
   [(set_attr "flags" "x")]
   )
 
-(define_insn_and_split "movhicc_eq_<mode>"
+(define_insn_and_split "movhicc_<code>_<mode>"
   [(set (match_operand:HI 0 "register_operand" "=R0w")
-        (if_then_else:HI (eq:HI (match_operand:QHPSI 1 "mra_operand" "RraSd")
-				(match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
+        (if_then_else:HI (eqne_cond:HI (match_operand:QHPSI 1 "mra_operand" "RraSd")
+				       (match_operand:QHPSI 2 "mrai_operand" "RraSdi"))
 			  (match_operand:QI 3 "const_int_operand" "")
 			  (match_operand:QI 4 "const_int_operand" "")))]
   "TARGET_A24"
@@ -219,7 +219,7 @@
 	(compare (match_dup 1)
 		 (match_dup 2)))
    (set (match_dup 0)
-        (if_then_else:HI (eq:HI (reg:CC FLG_REGNO) (const_int 0))
+        (if_then_else:HI (eqne_cond:HI (reg:CC FLG_REGNO) (const_int 0))
 			 (match_dup 3)
 			 (match_dup 4)))]
   ""
Index: gcc/config/m32c/m32c.md
===================================================================
--- gcc/config/m32c/m32c.md	(branch cond-optab)
+++ gcc/config/m32c/m32c.md	(working copy)
@@ -60,6 +60,7 @@
 (define_mode_iterator QHSI [QI HI (SI "TARGET_A24")])
 (define_mode_attr bwl [(QI "b") (HI "w") (PSI "l") (SI "l")])
 
+(define_code_iterator eqne_cond [eq ne])
 
 
 (define_insn "nop"
Index: gcc/config/sh/sh.md
===================================================================
--- gcc/config/sh/sh.md	(branch cond-optab)
+++ gcc/config/sh/sh.md	(working copy)
@@ -736,7 +736,7 @@
   [(set (pc)
 	(if_then_else (match_operator 0 "comparison_operator"
 			[(match_operand:DI 1 "arith_operand" "r,r")
-			 (match_operand:DI 2 "arith_operand" "rN,i")])
+			 (match_operand:DI 2 "arith_operand" "rN,I08")])
 		      (label_ref (match_operand 3 "" ""))
 		      (pc)))
    (clobber (match_scratch:SI 4 "=X,&r"))
@@ -9197,7 +9197,7 @@ mov.l\\t1f,r0\\n\\
 (define_expand "cstoresi4"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operator:SI 1 "comparison_operator"
-	 [(match_operand:SI 2 "arith_operand" "")
+	 [(match_operand:SI 2 "cmpsi_operand" "")
 	  (match_operand:SI 3 "arith_operand" "")]))]
   "TARGET_SH1 || TARGET_SHMEDIA"
   "if (TARGET_SHMEDIA)
@@ -9207,13 +9207,13 @@ mov.l\\t1f,r0\\n\\
       DONE;
     }
 
-   if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[0]) == NE)
+   if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
        && sh_expand_t_scc (operands))
      DONE;
 
    if (! currently_expanding_to_rtl)
      FAIL;
-   
+
    sh_emit_compare_and_set (operands, SImode);
    DONE;
 ")
@@ -9231,7 +9231,7 @@ mov.l\\t1f,r0\\n\\
       DONE;
     }
 
-   if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[0]) == NE)
+   if ((GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)
        && sh_expand_t_scc (operands))
      DONE;
 
Index: gcc/config/m68hc11/m68hc11.c
===================================================================
--- gcc/config/m68hc11/m68hc11.c	(branch cond-optab)
+++ gcc/config/m68hc11/m68hc11.c	(working copy)
@@ -3881,7 +3881,11 @@ m68hc11_notice_update_cc (rtx exp, rtx i
 	{
 	  cc_status.flags = 0;
 	  cc_status.value1 = XEXP (exp, 0);
-	  cc_status.value2 = XEXP (exp, 1);
+	  if (GET_CODE (XEXP (exp, 1)) == COMPARE
+	      && XEXP (XEXP (exp, 1), 1) == CONST0_RTX (GET_MODE (XEXP (XEXP (exp, 1), 0))))
+	    cc_status.value2 = XEXP (XEXP (exp, 1), 0);
+	  else
+	    cc_status.value2 = XEXP (exp, 1);
 	}
       else
 	{
Index: gcc/final.c
===================================================================
--- gcc/final.c	(branch cond-optab)
+++ gcc/final.c	(working copy)
@@ -2316,10 +2316,13 @@ final_scan_insn (rtx insn, FILE *file, i
 		&& GET_CODE (SET_DEST (set)) == CC0
 		&& insn != last_ignored_compare)
 	      {
-		rtx src = SET_SRC (set);
+		rtx src1, src2;
 		if (GET_CODE (SET_SRC (set)) == SUBREG)
 		  SET_SRC (set) = alter_subreg (&SET_SRC (set));
-		else if (GET_CODE (SET_SRC (set)) == COMPARE)
+
+		src1 = SET_SRC (set);
+		src2 = NULL_RTX;
+		if (GET_CODE (SET_SRC (set)) == COMPARE)
 		  {
 		    if (GET_CODE (XEXP (SET_SRC (set), 0)) == SUBREG)
 		      XEXP (SET_SRC (set), 0)
@@ -2329,12 +2332,16 @@ final_scan_insn (rtx insn, FILE *file, i
 			= alter_subreg (&XEXP (SET_SRC (set), 1));
 		    if (XEXP (SET_SRC (set), 1)
 			== CONST0_RTX (GET_MODE (XEXP (SET_SRC (set), 0))))
-		      src = XEXP (SET_SRC (set), 0);
+		      src2 = XEXP (SET_SRC (set), 0);
 		  }
 		if ((cc_status.value1 != 0
-		     && rtx_equal_p (src, cc_status.value1))
+		     && rtx_equal_p (src1, cc_status.value1))
 		    || (cc_status.value2 != 0
-			&& rtx_equal_p (src, cc_status.value2)))
+			&& rtx_equal_p (src1, cc_status.value2))
+		    || (src2 != 0 && cc_status.value1 != 0
+		        && rtx_equal_p (src2, cc_status.value1))
+		    || (src2 != 0 && cc_status.value2 != 0
+			&& rtx_equal_p (src2, cc_status.value2)))
 		  {
 		    /* Don't delete insn if it has an addressing side-effect.  */
 		    if (! FIND_REG_INC_NOTE (insn, NULL_RTX)
@@ -2348,9 +2355,7 @@ final_scan_insn (rtx insn, FILE *file, i
 		  }
 	      }
 	  }
-#endif
 
-#ifdef HAVE_cc0
 	/* If this is a conditional branch, maybe modify it
 	   if the cc's are in a nonstandard state
 	   so that it accomplishes the same thing that it would

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]