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Re: [PATCH] New MIPS interrupt handler patch


Ian Lance Taylor wrote:
"Fu, Chao-Ying" <fu@mips.com> writes:

+#ifdef FINAL_POSTSCAN_INSN
>> +     FINAL_POSTSCAN_INSN (insn, ops,insn_noperands);
>> +#endif

I know we have FINAL_PRESCAN_INSN, but I sort of hate to see us introduce another target macro. We are supposedly trying to move
toward function pointers in the target structure (target.h,
target-def.h). How about doing that instead?



I am fine with function pointers. Here is the updated patch that uses the original "FINAL_PRESCAN_INSN" and the new "final_postscan_insn" function pointer. Thanks!

Regards,
Chao-ying

gcc/ChangeLog
2009-04-09  Chao-ying Fu  <fu@mips.com>

	* doc/tm.texi (Instruction Output): Document
	TARGET_ASM_FINAL_POSTSCAN_INSN.
	* target.h (final_postscan_insn): New field in asm_out.
	* target-def.h (TARGET_ASM_FINAL_POSTSCAN_INSN): New define.
	(TARGET_ASM_OUT): Add TARGET_ASM_FINAL_POSTSCAN_INSN.
	* final.c (final_scan_insn): Call
	targetm.asm_out.final_postscan_insn after outputting
	an asm macro and a normal instruction.

	* config/mips/mips.h (FINAL_PRESCAN_INSN): New define.
	* config/mips/mips-protos.h (mips_final_prescan_insn):
	Declare.
	* config/mips/mips.c (mips_at_reg_p): New for_each_rtx callback.
	(mips_final_prescan_insn, mips_final_postscan_insn): New
	functions.
	(TARGET_ASM_FINAL_POSTSCAN_INSN): New define.

gcc/testsuite/ChangeLog
2009-04-09  Chao-ying Fu  <fu@mips.com>

	* gcc.target/mips/interrupt_handler.c: Change from compile to
	assemble.
	
Index: doc/tm.texi
===================================================================
--- doc/tm.texi	(revision 145780)
+++ doc/tm.texi	(working copy)
@@ -8193,6 +8193,19 @@ writing conditional output routines in t
 If this macro is not defined, it is equivalent to a null statement.
 @end defmac

+@deftypefn {Target Hook} void TARGET_ASM_FINAL_POSTSCAN_INSN (FILE
*@var{FILE}, rtx @var{insn}, rtx *@var{opvec}, int @var{noperands})
+If defined, this target hook is a function which is executed just after the
+output of assembler code for @var{insn}, to change the mode of the
assembler
+if necessary.
+
+Here the argument @var{opvec} is the vector containing the operands
+extracted from @var{insn}, and @var{noperands} is the number of
+elements of the vector which contain meaningful data for this insn.
+The contents of this vector are what was used to convert the insn
+template into assembler code, so you can change the assembler mode
+by checking the contents of the vector.
+@end deftypefn
+
 @defmac PRINT_OPERAND (@var{stream}, @var{x}, @var{code})
 A C compound statement to output to stdio stream @var{stream} the
 assembler syntax for an instruction operand @var{x}.  @var{x} is an
Index: target.h
===================================================================
--- target.h	(revision 145780)
+++ target.h	(working copy)
@@ -245,6 +245,8 @@ struct gcc_target
     /* Output a DTP-relative reference to a TLS symbol.  */
     void (*output_dwarf_dtprel) (FILE *file, int size, rtx x);

+    /* Some target machines need to postscan each insn after it is
output.  */
+    void (*final_postscan_insn) (FILE *, rtx, rtx *, int);
   } asm_out;

   /* Functions relating to instruction scheduling.  */
Index: final.c
===================================================================
--- final.c	(revision 145780)
+++ final.c	(working copy)
@@ -2235,6 +2235,10 @@ final_scan_insn (rtx insn, FILE *file, i
 #endif
 	      }

+	    if (targetm.asm_out.final_postscan_insn)
+	      targetm.asm_out.final_postscan_insn (file, insn, ops,
+						   insn_noperands);
+
 	    this_is_asm_operands = 0;
 	    break;
 	  }
@@ -2637,6 +2641,12 @@ final_scan_insn (rtx insn, FILE *file, i
 	/* Output assembler code from the template.  */
 	output_asm_insn (templ, recog_data.operand);

+	/* Some target machines need to postscan each insn after
+	   it is output.  */
+	if (targetm.asm_out.final_postscan_insn)
+	  targetm.asm_out.final_postscan_insn (file, insn, recog_data.operand,
+					       recog_data.n_operands);
+
 	/* If necessary, report the effect that the instruction has on
 	   the unwind info.   We've already done this for delay slots
 	   and call instructions.  */
Index: testsuite/gcc.target/mips/interrupt_handler.c
===================================================================
--- testsuite/gcc.target/mips/interrupt_handler.c	(revision 145780)
+++ testsuite/gcc.target/mips/interrupt_handler.c	(working copy)
@@ -1,5 +1,5 @@
 /* Test attributes for interrupt handlers */
-/* { dg-do compile } */
+/* { dg-do assemble } */
 /* { dg-options "-mips32r2 -msoft-float" } */

 void f () { }
Index: target-def.h
===================================================================
--- target-def.h	(revision 145780)
+++ target-def.h	(working copy)
@@ -236,6 +236,10 @@
 #define TARGET_ASM_OUTPUT_DWARF_DTPREL NULL
 #endif

+#ifndef TARGET_ASM_FINAL_POSTSCAN_INSN
+#define TARGET_ASM_FINAL_POSTSCAN_INSN NULL
+#endif
+
 #ifndef TARGET_ASM_RECORD_GCC_SWITCHES
 #define TARGET_ASM_RECORD_GCC_SWITCHES NULL
 #endif
@@ -291,7 +295,8 @@
 			TARGET_ASM_RECORD_GCC_SWITCHES,		\
 			TARGET_ASM_RECORD_GCC_SWITCHES_SECTION,	\
 			TARGET_ASM_OUTPUT_ANCHOR,		\
-			TARGET_ASM_OUTPUT_DWARF_DTPREL}
+			TARGET_ASM_OUTPUT_DWARF_DTPREL,		\
+			TARGET_ASM_FINAL_POSTSCAN_INSN}

 /* Scheduler hooks.  All of these default to null pointers, which
    haifa-sched.c looks for and handles.  */
Index: config/mips/mips-protos.h
===================================================================
--- config/mips/mips-protos.h	(revision 145780)
+++ config/mips/mips-protos.h	(working copy)
@@ -333,5 +333,6 @@ extern void mips_expand_atomic_qihi (uni
 extern void mips_expand_vector_init (rtx, rtx);

 extern bool mips_epilogue_uses (unsigned int);
+extern void mips_final_prescan_insn (rtx, rtx *, int);

 #endif /* ! GCC_MIPS_PROTOS_H */
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c	(revision 145780)
+++ config/mips/mips.c	(working copy)
@@ -14697,6 +14697,41 @@ mips_epilogue_uses (unsigned int regno)

   return false;
 }
+
+/* A for_each_rtx callback.  Stop the search if *X is an AT register.  */
+
+static int
+mips_at_reg_p (rtx *x, void *data ATTRIBUTE_UNUSED)
+{
+  return GET_CODE (*x) == REG && REGNO (*x) == AT_REGNUM;
+}
+
+
+/* Implement FINAL_PRESCAN_INSN.  */
+
+void
+mips_final_prescan_insn (rtx insn, rtx *opvec, int noperands)
+{
+  int i;
+  if (recog_memoized (insn) >= 0)
+    for (i = 0; i < noperands; i++)
+      if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
+	if (set_noat++ == 0)
+	  fprintf (asm_out_file, "\t.set\tnoat\n");
+}
+
+/* Implement FINAL_POSTSCAN_INSN.  */
+
+void
+mips_final_postscan_insn (FILE *file, rtx insn, rtx *opvec, int noperands)
+{
+  int i;
+  if (recog_memoized (insn) >= 0)
+    for (i = 0; i < noperands; i++)
+      if (for_each_rtx (&opvec[i], mips_at_reg_p, NULL))
+	if (--set_noat == 0)
+	  fprintf (file, "\t.set\tat\n");
+}
 
 /* Initialize the GCC target structure.  */
 #undef TARGET_ASM_ALIGNED_HI_OP
@@ -14865,6 +14900,9 @@ mips_epilogue_uses (unsigned int regno)
 #undef TARGET_IRA_COVER_CLASSES
 #define TARGET_IRA_COVER_CLASSES mips_ira_cover_classes

+#undef TARGET_ASM_FINAL_POSTSCAN_INSN
+#define TARGET_ASM_FINAL_POSTSCAN_INSN mips_final_postscan_insn
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 #include "gt-mips.h"
Index: config/mips/mips.h
===================================================================
--- config/mips/mips.h	(revision 145780)
+++ config/mips/mips.h	(working copy)
@@ -3459,3 +3459,8 @@ extern enum mips_code_readable_setting m

 /* Enable querying of DFA units.  */
 #define CPU_UNITS_QUERY 1
+
+/* For an instruction that accesses $1 (AT), we need to output ".set noat"
+   before the instruction, and output ".set at" after the instruction.  */
+#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS)	\
+  mips_final_prescan_insn (INSN, OPVEC, NOPERANDS);

# The -mfp64 option is only valid in conjunction with -mips32r2.


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