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[patch, ia64, committed] Avoid extra register copies
- From: Steve Ellcey <sje at cup dot hp dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 3 Apr 2009 16:39:10 -0700 (PDT)
- Subject: [patch, ia64, committed] Avoid extra register copies
- Reply-to: sje at cup dot hp dot com
This IA64 patch changes the machine descriptions that use the
fr_register_operand predicate for an input operand to use the
fr_reg_or_fp01_operand instead. This will match the constants 0 and 1
which are always available in registers f0 and f1 and prevent some
unneccessary copying from f0/f1 to another floating point register.
Some descriptions were already using this predicate, I went through and
changed the rest to make them consistent. Some of these may never be
needed because we should optimize them away before we get to code
generation but others like 1/x or max(1,x) now avoid an uneeded reg to
reg copy.
Tested on IA64 HP-UX and Linux with no regressions and checked in.
Steve Ellcey
sje@cup.hp.com
2009-04-03 Steve Ellcey <sje@cup.hp.com>
* config/ia64/ia64.md (extendsfdf2, extendsfxf2, extenddfxf2,
truncdfsf2, truncxfsf2, truncxfdf2, floatdixf2, fix_truncsfdi2,
fix_truncdfdi2, fix_truncxfdi2, fix_truncxfdi2_alts, floatunsdisf2,
floatunsdidf2, floatunsdixf2, fixuns_truncsfdi2, fixuns_truncdfdi2,
fixuns_truncxfdi2, fixuns_truncxfdi2_alts, divsi3_internal,
smuldi3_highpart, umuldi3_highpart, ctzdi2, *getf_exp_xf,
divdi3_internal_lat, divdi3_internal_thr, mulditi3, *mulditi3_internal,
umulditi3, *umulditi3_internal, addsf3, mulsf3, abssf2, negsf2,
*nabssf2, sminsf3, smaxsf3, *maddsf4, *msubsf4, *nmulsf3, *nmaddsf4,
*nmaddsf4_alts, divsf3, *sqrt_approx, sqrtsf2, sqrtsf2_internal_thr,
adddf3, *adddf3_trunc, muldf3, *muldf3_trunc, absdf2, negdf2, *nabsdf2,
smindf3, smaxdf3, *madddf4, *madddf4_trunc, *msubdf4, *msubdf4_trunc,
*nmuldf3, *nmuldf3_trunc, *nmadddf4, *nmadddf4_alts, *nmadddf4_truncsf,
*nmadddf4_truncsf_alts, divdf3, sqrtdf2, sqrtdf2_internal_thr, divxf3,
sqrtxf2, sqrtxf2_internal_thr, *recip_approx):
Use fr_reg_or_fp01_operand instead of fr_register_operand
* config/ia64/div.md (extend<mode>rf2, truncrf<mode>2,
recip_approx_rf, divsf3_internal_thr, divsf3_internal_lat,
divdf3_internal_thr, divdf3_internal_lat divxf3_internal): Ditto.
Index: config/ia64/ia64.md
===================================================================
--- config/ia64/ia64.md (revision 145520)
+++ config/ia64/ia64.md (working copy)
@@ -1188,134 +1188,134 @@ (define_insn "zero_extendsidi2"
(define_insn "extendsfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (float_extend:DF (match_operand:SF 1 "fr_register_operand" "f")))]
+ (float_extend:DF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fnorm.d %0 = %1"
+ "fnorm.d %0 = %F1"
[(set_attr "itanium_class" "fmac")])
(define_insn "extendsfxf2"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
- (float_extend:XF (match_operand:SF 1 "fr_register_operand" "f")))]
+ (float_extend:XF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fnorm %0 = %1"
+ "fnorm %0 = %F1"
[(set_attr "itanium_class" "fmac")])
(define_insn "extenddfxf2"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
- (float_extend:XF (match_operand:DF 1 "fr_register_operand" "f")))]
+ (float_extend:XF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fnorm %0 = %1"
+ "fnorm %0 = %F1"
[(set_attr "itanium_class" "fmac")])
(define_insn "truncdfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (float_truncate:SF (match_operand:DF 1 "fr_register_operand" "f")))]
+ (float_truncate:SF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fnorm.s %0 = %1"
+ "fnorm.s %0 = %F1"
[(set_attr "itanium_class" "fmac")])
(define_insn "truncxfsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (float_truncate:SF (match_operand:XF 1 "fr_register_operand" "f")))]
+ (float_truncate:SF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fnorm.s %0 = %1"
+ "fnorm.s %0 = %F1"
[(set_attr "itanium_class" "fmac")])
(define_insn "truncxfdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (float_truncate:DF (match_operand:XF 1 "fr_register_operand" "f")))]
+ (float_truncate:DF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fnorm.d %0 = %1"
+ "fnorm.d %0 = %F1"
[(set_attr "itanium_class" "fmac")])
;; Convert between signed integer types and floating point.
(define_insn "floatdixf2"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
- (float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
+ (float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.xf %0 = %1"
+ "fcvt.xf %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
+ (fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.fx.trunc %0 = %1"
+ "fcvt.fx.trunc %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncdfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
+ (fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.fx.trunc %0 = %1"
+ "fcvt.fx.trunc %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncxfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
+ (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.fx.trunc %0 = %1"
+ "fcvt.fx.trunc %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fix_truncxfdi2_alts"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
+ (fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))
(use (match_operand:SI 2 "const_int_operand" ""))]
""
- "fcvt.fx.trunc.s%2 %0 = %1"
+ "fcvt.fx.trunc.s%2 %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
;; Convert between unsigned integer types and floating point.
(define_insn "floatunsdisf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (unsigned_float:SF (match_operand:DI 1 "fr_register_operand" "f")))]
+ (unsigned_float:SF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.xuf.s %0 = %1"
+ "fcvt.xuf.s %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "floatunsdidf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (unsigned_float:DF (match_operand:DI 1 "fr_register_operand" "f")))]
+ (unsigned_float:DF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.xuf.d %0 = %1"
+ "fcvt.xuf.d %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "floatunsdixf2"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
- (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "f")))]
+ (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.xuf %0 = %1"
+ "fcvt.xuf %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_truncsfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (unsigned_fix:DI (match_operand:SF 1 "fr_register_operand" "f")))]
+ (unsigned_fix:DI (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.fxu.trunc %0 = %1"
+ "fcvt.fxu.trunc %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_truncdfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (unsigned_fix:DI (match_operand:DF 1 "fr_register_operand" "f")))]
+ (unsigned_fix:DI (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.fxu.trunc %0 = %1"
+ "fcvt.fxu.trunc %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_truncxfdi2"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))]
+ (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fcvt.fxu.trunc %0 = %1"
+ "fcvt.fxu.trunc %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
(define_insn "fixuns_truncxfdi2_alts"
[(set (match_operand:DI 0 "fr_register_operand" "=f")
- (unsigned_fix:DI (match_operand:XF 1 "fr_register_operand" "f")))
+ (unsigned_fix:DI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))
(use (match_operand:SI 2 "const_int_operand" ""))]
""
- "fcvt.fxu.trunc.s%2 %0 = %1"
+ "fcvt.fxu.trunc.s%2 %0 = %F1"
[(set_attr "itanium_class" "fcvtfx")])
;; ::::::::::::::::::::
@@ -2295,8 +2295,8 @@ (define_expand "umodsi3"
(define_insn_and_split "divsi3_internal"
[(set (match_operand:XF 0 "fr_register_operand" "=&f")
- (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
- (match_operand:XF 2 "fr_register_operand" "f"))))
+ (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG"))))
(clobber (match_scratch:XF 4 "=&f"))
(clobber (match_scratch:XF 5 "=&f"))
(clobber (match_scratch:BI 6 "=c"))
@@ -2460,12 +2460,12 @@ (define_insn "smuldi3_highpart"
(truncate:DI
(lshiftrt:TI
(mult:TI (sign_extend:TI
- (match_operand:DI 1 "fr_register_operand" "f"))
+ (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
(sign_extend:TI
- (match_operand:DI 2 "fr_register_operand" "f")))
+ (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG")))
(const_int 64))))]
""
- "xmpy.h %0 = %1, %2"
+ "xmpy.h %0 = %F1, %F2"
[(set_attr "itanium_class" "xmpy")])
(define_insn "umuldi3_highpart"
@@ -2473,12 +2473,12 @@ (define_insn "umuldi3_highpart"
(truncate:DI
(lshiftrt:TI
(mult:TI (zero_extend:TI
- (match_operand:DI 1 "fr_register_operand" "f"))
+ (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
(zero_extend:TI
- (match_operand:DI 2 "fr_register_operand" "f")))
+ (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG")))
(const_int 64))))]
""
- "xmpy.hu %0 = %1, %2"
+ "xmpy.hu %0 = %F1, %F2"
[(set_attr "itanium_class" "xmpy")])
(define_insn "negdi2"
@@ -2574,7 +2574,7 @@ (define_expand "ctzdi2"
;; Note the computation here is op0 = 63 - (exp - 0xffff).
(define_expand "clzdi2"
[(set (match_dup 2)
- (unsigned_float:XF (match_operand:DI 1 "fr_register_operand" "")))
+ (unsigned_float:XF (match_operand:DI 1 "fr_reg_or_fp01_operand" "")))
(set (match_dup 3)
(unspec:DI [(match_dup 2)] UNSPEC_GETF_EXP))
(set (match_dup 4) (const_int 65598))
@@ -2603,10 +2603,10 @@ (define_insn "bswapdi2"
(define_insn "*getf_exp_xf"
[(set (match_operand:DI 0 "gr_register_operand" "=r")
- (unspec:DI [(match_operand:XF 1 "fr_register_operand" "f")]
+ (unspec:DI [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")]
UNSPEC_GETF_EXP))]
""
- "getf.exp %0 = %1"
+ "getf.exp %0 = %F1"
[(set_attr "itanium_class" "frfr")])
(define_expand "divdi3"
@@ -2709,8 +2709,8 @@ (define_expand "umoddi3"
(define_insn_and_split "divdi3_internal_lat"
[(set (match_operand:XF 0 "fr_register_operand" "=&f")
- (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
- (match_operand:XF 2 "fr_register_operand" "f"))))
+ (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG"))))
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:XF 4 "=&f"))
(clobber (match_scratch:XF 5 "=&f"))
@@ -2770,8 +2770,8 @@ (define_insn_and_split "divdi3_internal_
(define_insn_and_split "divdi3_internal_thr"
[(set (match_operand:XF 0 "fr_register_operand" "=&f")
- (float:XF (div:SI (match_operand:XF 1 "fr_register_operand" "f")
- (match_operand:XF 2 "fr_register_operand" "f"))))
+ (float:XF (div:SI (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG"))))
(clobber (match_scratch:XF 3 "=&f"))
(clobber (match_scratch:XF 4 "=f"))
(clobber (match_scratch:BI 5 "=c"))]
@@ -2934,18 +2934,18 @@ (define_split
(define_expand "mulditi3"
[(set (match_operand:TI 0 "fr_register_operand" "")
(mult:TI (sign_extend:TI
- (match_operand:DI 1 "fr_register_operand" ""))
+ (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))
(sign_extend:TI
- (match_operand:DI 2 "fr_register_operand" ""))))]
+ (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))]
""
"")
(define_insn_and_split "*mulditi3_internal"
[(set (match_operand:TI 0 "fr_register_operand" "=&f")
(mult:TI (sign_extend:TI
- (match_operand:DI 1 "fr_register_operand" "%f"))
+ (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
(sign_extend:TI
- (match_operand:DI 2 "fr_register_operand" "f"))))]
+ (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))]
""
"#"
"reload_completed"
@@ -2964,18 +2964,18 @@ (define_insn_and_split "*mulditi3_intern
(define_expand "umulditi3"
[(set (match_operand:TI 0 "fr_register_operand" "")
(mult:TI (zero_extend:TI
- (match_operand:DI 1 "fr_register_operand" ""))
+ (match_operand:DI 1 "fr_reg_or_fp01_operand" ""))
(zero_extend:TI
- (match_operand:DI 2 "fr_register_operand" ""))))]
+ (match_operand:DI 2 "fr_reg_or_fp01_operand" ""))))]
""
"")
(define_insn_and_split "*umulditi3_internal"
[(set (match_operand:TI 0 "fr_register_operand" "=&f")
(mult:TI (zero_extend:TI
- (match_operand:DI 1 "fr_register_operand" "%f"))
+ (match_operand:DI 1 "fr_reg_or_fp01_operand" "fG"))
(zero_extend:TI
- (match_operand:DI 2 "fr_register_operand" "f"))))]
+ (match_operand:DI 2 "fr_reg_or_fp01_operand" "fG"))))]
""
"#"
"reload_completed"
@@ -3020,10 +3020,10 @@ (define_insn_and_split "negti2"
(define_insn "addsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (plus:SF (match_operand:SF 1 "fr_register_operand" "%f")
+ (plus:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
- "fadd.s %0 = %1, %F2"
+ "fadd.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "subsf3"
@@ -3036,31 +3036,31 @@ (define_insn "subsf3"
(define_insn "mulsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (mult:SF (match_operand:SF 1 "fr_register_operand" "%f")
- (match_operand:SF 2 "fr_register_operand" "f")))]
+ (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
- "fmpy.s %0 = %1, %2"
+ "fmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "abssf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (abs:SF (match_operand:SF 1 "fr_register_operand" "f")))]
+ (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fabs %0 = %1"
+ "fabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (neg:SF (match_operand:SF 1 "fr_register_operand" "f")))]
+ (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fneg %0 = %1"
+ "fneg %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabssf2"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (neg:SF (abs:SF (match_operand:SF 1 "fr_register_operand" "f"))))]
+ (neg:SF (abs:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fnegabs %0 = %1"
+ "fnegabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "copysignsf3"
@@ -3083,69 +3083,69 @@ (define_insn "*ncopysignsf3"
(define_insn "sminsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (smin:SF (match_operand:SF 1 "fr_register_operand" "f")
+ (smin:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
- "fmin %0 = %1, %F2"
+ "fmin %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "smaxsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (smax:SF (match_operand:SF 1 "fr_register_operand" "f")
+ (smax:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")))]
""
- "fmax %0 = %1, %F2"
+ "fmax %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*maddsf4"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (plus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
- (match_operand:SF 2 "fr_register_operand" "f"))
+ (plus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
- "fma.s %0 = %1, %2, %F3"
+ "fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubsf4"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (minus:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
- (match_operand:SF 2 "fr_register_operand" "f"))
+ (minus:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")))]
""
- "fms.s %0 = %1, %2, %F3"
+ "fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmulsf3"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
- (neg:SF (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
- (match_operand:SF 2 "fr_register_operand" "f"))))]
+ (neg:SF (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fnmpy.s %0 = %1, %2"
+ "fnmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddsf4"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
- (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
- (match_operand:SF 2 "fr_register_operand" "f"))))]
+ (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fnma.s %0 = %1, %2, %F3"
+ "fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmaddsf4_alts"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(minus:SF (match_operand:SF 3 "fr_reg_or_fp01_operand" "fG")
- (mult:SF (match_operand:SF 1 "fr_register_operand" "f")
- (match_operand:SF 2 "fr_register_operand" "f"))))
+ (mult:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
- "fnma.s.s%4 %0 = %1, %2, %F3"
+ "fnma.s.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_expand "divsf3"
[(set (match_operand:SF 0 "fr_register_operand" "")
- (div:SF (match_operand:SF 1 "fr_register_operand" "")
- (match_operand:SF 2 "fr_register_operand" "")))]
+ (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
@@ -3162,7 +3162,7 @@ (define_expand "divsf3"
(define_insn "*sqrt_approx"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
(div:XF (const_int 1)
- (unspec:XF [(match_operand:XF 2 "fr_register_operand" "f")]
+ (unspec:XF [(match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")]
UNSPEC_FR_SQRT_RECIP_APPROX_RES)))
(set (match_operand:BI 1 "register_operand" "=c")
(unspec:BI [(match_dup 2)] UNSPEC_FR_SQRT_RECIP_APPROX))
@@ -3182,7 +3182,7 @@ (define_insn "setf_exp_xf"
(define_expand "sqrtsf2"
[(set (match_operand:SF 0 "fr_register_operand" "=&f")
- (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))]
+ (sqrt:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))]
"TARGET_INLINE_SQRT"
{
rtx insn;
@@ -3205,7 +3205,7 @@ (define_expand "sqrtsf2"
(define_insn_and_split "sqrtsf2_internal_thr"
[(set (match_operand:SF 0 "fr_register_operand" "=&f")
- (sqrt:SF (match_operand:SF 1 "fr_register_operand" "f")))
+ (sqrt:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")))
;; Register r2 in optimization guide.
(clobber (match_scratch:DI 2 "=r"))
;; Register f8 in optimization guide
@@ -3316,19 +3316,19 @@ (define_insn_and_split "sqrtsf2_internal
(define_insn "adddf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
+ (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
- "fadd.d %0 = %1, %F2"
+ "fadd.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*adddf3_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (plus:DF (match_operand:DF 1 "fr_register_operand" "%f")
+ (plus:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fadd.s %0 = %1, %F2"
+ "fadd.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "subdf3"
@@ -3350,40 +3350,40 @@ (define_insn "*subdf3_trunc"
(define_insn "muldf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f")))]
+ (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
- "fmpy.d %0 = %1, %2"
+ "fmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*muldf3_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f"))))]
+ (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fmpy.s %0 = %1, %2"
+ "fmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "absdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (abs:DF (match_operand:DF 1 "fr_register_operand" "f")))]
+ (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fabs %0 = %1"
+ "fabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "negdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (neg:DF (match_operand:DF 1 "fr_register_operand" "f")))]
+ (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
""
- "fneg %0 = %1"
+ "fneg %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*nabsdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (neg:DF (abs:DF (match_operand:DF 1 "fr_register_operand" "f"))))]
+ (neg:DF (abs:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fnegabs %0 = %1"
+ "fnegabs %0 = %F1"
[(set_attr "itanium_class" "fmisc")])
(define_insn "copysigndf3"
@@ -3406,119 +3406,119 @@ (define_insn "*ncopysigndf3"
(define_insn "smindf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (smin:DF (match_operand:DF 1 "fr_register_operand" "f")
+ (smin:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
- "fmin %0 = %1, %F2"
+ "fmin %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "smaxdf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (smax:DF (match_operand:DF 1 "fr_register_operand" "f")
+ (smax:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
(match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))]
""
- "fmax %0 = %1, %F2"
+ "fmax %0 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")])
(define_insn "*madddf4"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f"))
+ (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
- "fma.d %0 = %1, %2, %F3"
+ "fma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*madddf4_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (plus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f"))
+ (plus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fma.s %0 = %1, %2, %F3"
+ "fma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubdf4"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f"))
+ (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")))]
""
- "fms.d %0 = %1, %2, %F3"
+ "fms.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*msubdf4_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (minus:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f"))
+ (minus:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))
(match_operand:DF 3 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fms.s %0 = %1, %2, %F3"
+ "fms.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmuldf3"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
- (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f"))))]
+ (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fnmpy.d %0 = %1, %2"
+ "fnmpy.d %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmuldf3_trunc"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
- (neg:DF (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f")))))]
+ (neg:DF (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))]
""
- "fnmpy.s %0 = %1, %2"
+ "fnmpy.s %0 = %F1, %F2"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmadddf4"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
- (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f"))))]
+ (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))]
""
- "fnma.d %0 = %1, %2, %F3"
+ "fnma.d %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmadddf4_alts"
[(set (match_operand:DF 0 "fr_register_operand" "=f")
(minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
- (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f"))))
+ (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG"))))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
- "fnma.d.s%4 %0 = %1, %2, %F3"
+ "fnma.d.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmadddf4_truncsf"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
(minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
- (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f")))))]
+ (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))]
""
- "fnma.s %0 = %1, %2, %F3"
+ "fnma.s %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_insn "*nmadddf4_truncsf_alts"
[(set (match_operand:SF 0 "fr_register_operand" "=f")
(float_truncate:SF
(minus:DF (match_operand:DF 3 "fr_reg_or_fp01_operand" "fG")
- (mult:DF (match_operand:DF 1 "fr_register_operand" "f")
- (match_operand:DF 2 "fr_register_operand" "f")))))
+ (mult:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")))))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
- "fnma.s.s%4 %0 = %1, %2, %F3"
+ "fnma.s.s%4 %0 = %F1, %F2, %F3"
[(set_attr "itanium_class" "fmac")])
(define_expand "divdf3"
[(set (match_operand:DF 0 "fr_register_operand" "")
- (div:DF (match_operand:DF 1 "fr_register_operand" "")
- (match_operand:DF 2 "fr_register_operand" "")))]
+ (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx insn;
@@ -3534,7 +3534,7 @@ (define_expand "divdf3"
(define_expand "sqrtdf2"
[(set (match_operand:DF 0 "fr_register_operand" "=&f")
- (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))]
+ (sqrt:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))]
"TARGET_INLINE_SQRT"
{
rtx insn;
@@ -3557,7 +3557,7 @@ (define_expand "sqrtdf2"
(define_insn_and_split "sqrtdf2_internal_thr"
[(set (match_operand:DF 0 "fr_register_operand" "=&f")
- (sqrt:DF (match_operand:DF 1 "fr_register_operand" "f")))
+ (sqrt:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")))
;; Register r2 in optimization guide.
(clobber (match_scratch:DI 2 "=r"))
;; Register f8 in optimization guide
@@ -4035,8 +4035,8 @@ (define_insn "*nmaddxf4_truncdf_alts"
(define_expand "divxf3"
[(set (match_operand:XF 0 "fr_register_operand" "")
- (div:XF (match_operand:XF 1 "fr_register_operand" "")
- (match_operand:XF 2 "fr_register_operand" "")))]
+ (div:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:XF 2 "fr_reg_or_fp01_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
/* There is only one divxf3 sequence, not two like for divsf and divdf. */
@@ -4048,7 +4048,7 @@ (define_expand "divxf3"
(define_expand "sqrtxf2"
[(set (match_operand:XF 0 "fr_register_operand" "=&f")
- (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))]
+ (sqrt:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))]
"TARGET_INLINE_SQRT"
{
rtx insn;
@@ -4071,7 +4071,7 @@ (define_expand "sqrtxf2"
(define_insn_and_split "sqrtxf2_internal_thr"
[(set (match_operand:XF 0 "fr_register_operand" "=&f")
- (sqrt:XF (match_operand:XF 1 "fr_register_operand" "f")))
+ (sqrt:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")))
;; Register r2 in optimization guide.
(clobber (match_scratch:DI 2 "=r"))
;; Register f8 in optimization guide
@@ -4214,14 +4214,14 @@ (define_insn_and_split "sqrtxf2_internal
(define_insn "*recip_approx"
[(set (match_operand:XF 0 "fr_register_operand" "=f")
(unspec:XF [(const_int 1)
- (match_operand:XF 3 "fr_register_operand" "f")]
+ (match_operand:XF 3 "fr_reg_or_fp01_operand" "fG")]
UNSPEC_FR_RECIP_APPROX_RES))
(set (match_operand:BI 1 "register_operand" "=c")
- (unspec:BI [(match_operand:XF 2 "fr_register_operand" "f")
+ (unspec:BI [(match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")
(match_dup 3)] UNSPEC_FR_RECIP_APPROX))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
- "frcpa.s%4 %0, %1 = %2, %3"
+ "frcpa.s%4 %0, %1 = %F2, %F3"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
Index: config/ia64/div.md
===================================================================
--- config/ia64/div.md (revision 145520)
+++ config/ia64/div.md (working copy)
@@ -162,7 +162,7 @@ (define_mode_iterator SDX_F [SF DF XF])
(define_insn "extend<mode>rf2"
[(set (match_operand:RF 0 "fr_register_operand" "=f")
- (float_extend:RF (match_operand:SDX_F 1 "fr_register_operand" "f")))]
+ (float_extend:RF (match_operand:SDX_F 1 "fr_reg_or_fp01_operand" "fG")))]
""
"#"
[(set_attr "itanium_class" "fmisc")
@@ -170,17 +170,22 @@ (define_insn "extend<mode>rf2"
(define_split
[(set (match_operand:RF 0 "fr_register_operand" "")
- (float_extend:RF (match_operand:SDX_F 1 "fr_register_operand" "")))]
+ (float_extend:RF (match_operand:SDX_F 1 "fr_reg_or_fp01_operand" "")))]
"reload_completed"
[(set (match_dup 0) (match_dup 2))]
{
- operands[2] = gen_rtx_REG (RFmode, REGNO (operands[1]));
+ if (operands[1] == CONST0_RTX (<MODE>mode))
+ operands[2] = gen_rtx_REG (RFmode, FR_REG (0));
+ else if (operands[1] == CONST1_RTX (<MODE>mode))
+ operands[2] = gen_rtx_REG (RFmode, FR_REG (1));
+ else
+ operands[2] = gen_rtx_REG (RFmode, REGNO (operands[1]));
})
(define_insn "truncrf<mode>2"
[(set (match_operand:SDX_F 0 "fr_register_operand" "=f")
- (float_truncate:SDX_F (match_operand:RF 1 "fr_register_operand" "f")))]
+ (float_truncate:SDX_F (match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")))]
""
"#"
[(set_attr "itanium_class" "fmisc")
@@ -188,25 +193,30 @@ (define_insn "truncrf<mode>2"
(define_split
[(set (match_operand:SDX_F 0 "fr_register_operand" "")
- (float_truncate:SDX_F (match_operand:RF 1 "fr_register_operand" "")))]
+ (float_truncate:SDX_F (match_operand:RF 1 "fr_reg_or_fp01_operand" "")))]
"reload_completed"
[(set (match_dup 0) (match_dup 2))]
{
- operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
+ if (operands[1] == CONST0_RTX (RFmode))
+ operands[2] = gen_rtx_REG (<MODE>mode, FR_REG (0));
+ else if (operands[1] == CONST1_RTX (RFmode))
+ operands[2] = gen_rtx_REG (<MODE>mode, FR_REG (1));
+ else
+ operands[2] = gen_rtx_REG (<MODE>mode, REGNO (operands[1]));
})
;; Reciprocal approximation
(define_insn "recip_approx_rf"
[(set (match_operand:RF 0 "fr_register_operand" "=f")
- (unspec:RF [(match_operand:RF 1 "fr_register_operand" "f")
- (match_operand:RF 2 "fr_register_operand" "f")]
+ (unspec:RF [(match_operand:RF 1 "fr_reg_or_fp01_operand" "fG")
+ (match_operand:RF 2 "fr_reg_or_fp01_operand" "fG")]
UNSPEC_FR_RECIP_APPROX_RES))
(set (match_operand:BI 3 "register_operand" "=c")
(unspec:BI [(match_dup 1) (match_dup 2)] UNSPEC_FR_RECIP_APPROX))
(use (match_operand:SI 4 "const_int_operand" ""))]
""
- "frcpa.s%4 %0, %3 = %1, %2"
+ "frcpa.s%4 %0, %3 = %F1, %F2"
[(set_attr "itanium_class" "fmisc")
(set_attr "predicable" "no")])
@@ -214,8 +224,8 @@ (define_insn "recip_approx_rf"
(define_expand "divsf3_internal_thr"
[(set (match_operand:SF 0 "fr_register_operand" "")
- (div:SF (match_operand:SF 1 "fr_register_operand" "")
- (match_operand:SF 2 "fr_register_operand" "")))]
+ (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx y = gen_reg_rtx (RFmode);
@@ -261,8 +271,8 @@ (define_expand "divsf3_internal_thr"
(define_expand "divsf3_internal_lat"
[(set (match_operand:SF 0 "fr_register_operand" "")
- (div:SF (match_operand:SF 1 "fr_register_operand" "")
- (match_operand:SF 2 "fr_register_operand" "")))]
+ (div:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx y = gen_reg_rtx (RFmode);
@@ -312,8 +322,8 @@ (define_expand "divsf3_internal_lat"
(define_expand "divdf3_internal_thr"
[(set (match_operand:DF 0 "fr_register_operand" "")
- (div:DF (match_operand:DF 1 "fr_register_operand" "")
- (match_operand:DF 2 "fr_register_operand" "")))]
+ (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx q_res = gen_reg_rtx (RFmode);
@@ -367,8 +377,8 @@ (define_expand "divdf3_internal_thr"
(define_expand "divdf3_internal_lat"
[(set (match_operand:DF 0 "fr_register_operand" "")
- (div:DF (match_operand:DF 1 "fr_register_operand" "")
- (match_operand:DF 2 "fr_register_operand" "")))]
+ (div:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx q_res = gen_reg_rtx (RFmode);
@@ -429,8 +439,8 @@ (define_expand "divdf3_internal_lat"
(define_expand "divxf3_internal"
[(set (match_operand:XF 0 "fr_register_operand" "")
- (div:XF (match_operand:XF 1 "fr_register_operand" "")
- (match_operand:XF 2 "fr_register_operand" "")))]
+ (div:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:XF 2 "fr_reg_or_fp01_operand" "")))]
"TARGET_INLINE_FLOAT_DIV"
{
rtx q_res = gen_reg_rtx (RFmode);