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[cond-optab] Convert ia64
- From: Paolo Bonzini <bonzini at gnu dot org>
- To: <gcc-patches at gcc dot gnu dot org>
- Date: Thu, 26 Mar 2009 04:35:49 -0400
- Subject: [cond-optab] Convert ia64
Like Blackfin, ia64 comparisons are all done in BImode, so the conversion
is not hard. I've not simplified things as much as I could, for example
by defining cbranchbi4 instructions like Blackfin does.
There are a lot of patterns to define here, nevertheless a few lines
are saved in this port too.
Paolo
2009-03-24 Paolo Bonzini <bonzini@gnu.org>
* config/ia64/ia64-protos.h (ia64_compare_op0, ia64_compare_op1):
Delete.
(ia64_expand_compare): Accept three rtx by reference and return void.
* config/ia64/ia64.c (ia64_compare_op0, ia64_compare_op1): Delete.
(ia64_expand_compare): Replace op0/op1 with *op0/*op1. Get code
from *expr. Update *expr with the BImode comparison to do.
* config/ia64/ia64.md (cmpbi, cmpsi, cmpdi, cmpsf, cmpdf, cmpxf,
cmptf, bCC, sCC, conditional_trap): Delete.
(cbranchbi4, cbranchsi4, cbranchdi4, cbranchsf4, cbranchdf4,
cbranchxf4, cbranchtf4, cstorebi4, cstoresi4, cstoredi4, cstoresf4,
cstoredf4, cstorexf4, cstoretf4, ctrapbi4, ctrapsi4, ctrapdi4,
ctrapsf4, ctrapdf4, ctrapxf4, ctraptf4): New.
* config/ia64/predicates.md (ia64_cbranch_operator): New.
Index: gcc/config/ia64/ia64-protos.h
===================================================================
--- gcc/config/ia64/ia64-protos.h (branch cond-optab)
+++ gcc/config/ia64/ia64-protos.h (working copy)
@@ -18,13 +18,6 @@ You should have received a copy of the G
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
-/* Variables defined in ia64.c. */
-
-#ifdef RTX_CODE
-extern GTY(()) rtx ia64_compare_op0;
-extern GTY(()) rtx ia64_compare_op1;
-#endif
-
/* Functions defined in ia64.c */
extern int bundling_p;
@@ -43,7 +36,7 @@ extern void ia64_emit_cond_move (rtx, rt
extern int ia64_depz_field_mask (rtx, rtx);
extern void ia64_split_tmode_move (rtx[]);
extern bool ia64_expand_movxf_movrf (enum machine_mode, rtx[]);
-extern rtx ia64_expand_compare (enum rtx_code, enum machine_mode);
+extern void ia64_expand_compare (rtx *, rtx *, rtx *);
extern void ia64_expand_vecint_cmov (rtx[]);
extern bool ia64_expand_vecint_minmax (enum rtx_code, enum machine_mode, rtx[]);
extern void ia64_expand_widen_sum (rtx[], bool);
Index: gcc/config/ia64/ia64.c
===================================================================
--- gcc/config/ia64/ia64.c (branch cond-optab)
+++ gcc/config/ia64/ia64.c (working copy)
@@ -63,11 +63,6 @@ along with GCC; see the file COPYING3.
ASM_OUTPUT_LABELREF. */
int ia64_asm_output_label = 0;
-/* Define the information needed to generate branch and scc insns. This is
- stored from the compare operation. */
-struct rtx_def * ia64_compare_op0;
-struct rtx_def * ia64_compare_op1;
-
/* Register names for ia64_expand_prologue. */
static const char * const ia64_reg_numbers[96] =
{ "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
@@ -1494,28 +1489,28 @@ ia64_expand_movxf_movrf (enum machine_mo
return false;
}
-/* Emit comparison instruction if necessary, returning the expression
- that holds the compare result in the proper mode. */
+/* Emit comparison instruction if necessary, replacing *EXPR, *OP0, *OP1
+ with the expression that holds the compare result (in VOIDmode). */
static GTY(()) rtx cmptf_libfunc;
-rtx
-ia64_expand_compare (enum rtx_code code, enum machine_mode mode)
+void
+ia64_expand_compare (rtx *expr, rtx *op0, rtx *op1)
{
- rtx op0 = ia64_compare_op0, op1 = ia64_compare_op1;
+ enum rtx_code code = GET_CODE (*expr);
rtx cmp;
/* If we have a BImode input, then we already have a compare result, and
do not need to emit another comparison. */
- if (GET_MODE (op0) == BImode)
+ if (GET_MODE (*op0) == BImode)
{
- gcc_assert ((code == NE || code == EQ) && op1 == const0_rtx);
- cmp = op0;
+ gcc_assert ((code == NE || code == EQ) && *op1 == const0_rtx);
+ cmp = *op0;
}
/* HPUX TFmode compare requires a library call to _U_Qfcmp, which takes a
magic number as its third argument, that indicates what to do.
The return value is an integer to be compared against zero. */
- else if (TARGET_HPUX && GET_MODE (op0) == TFmode)
+ else if (TARGET_HPUX && GET_MODE (*op0) == TFmode)
{
enum qfcmp_magic {
QCMP_INV = 1, /* Raise FP_INVALID on SNaN as a side effect. */
@@ -1527,7 +1522,7 @@ ia64_expand_compare (enum rtx_code code,
enum rtx_code ncode;
rtx ret, insns;
- gcc_assert (cmptf_libfunc && GET_MODE (op1) == TFmode);
+ gcc_assert (cmptf_libfunc && GET_MODE (*op1) == TFmode);
switch (code)
{
/* 1 = equal, 0 = not equal. Equality operators do
@@ -1552,7 +1547,7 @@ ia64_expand_compare (enum rtx_code code,
start_sequence ();
ret = emit_library_call_value (cmptf_libfunc, 0, LCT_CONST, DImode, 3,
- op0, TFmode, op1, TFmode,
+ *op0, TFmode, *op1, TFmode,
GEN_INT (magic), DImode);
cmp = gen_reg_rtx (BImode);
emit_insn (gen_rtx_SET (VOIDmode, cmp,
@@ -1563,18 +1558,20 @@ ia64_expand_compare (enum rtx_code code,
end_sequence ();
emit_libcall_block (insns, cmp, cmp,
- gen_rtx_fmt_ee (code, BImode, op0, op1));
+ gen_rtx_fmt_ee (code, BImode, *op0, *op1));
code = NE;
}
else
{
cmp = gen_reg_rtx (BImode);
emit_insn (gen_rtx_SET (VOIDmode, cmp,
- gen_rtx_fmt_ee (code, BImode, op0, op1)));
+ gen_rtx_fmt_ee (code, BImode, *op0, *op1)));
code = NE;
}
- return gen_rtx_fmt_ee (code, mode, cmp, const0_rtx);
+ *expr = gen_rtx_fmt_ee (code, VOIDmode, cmp, const0_rtx);
+ *op0 = cmp;
+ *op1 = const0_rtx;
}
/* Generate an integral vector comparison. Return true if the condition has
Index: gcc/config/ia64/ia64.md
===================================================================
--- gcc/config/ia64/ia64.md (branch cond-optab)
+++ gcc/config/ia64/ia64.md (working copy)
@@ -408,6 +408,7 @@
(set_attr "speculable2" "no, no, no, no, yes,no,no, no, no, yes,no, no, no, no, no, no, no, no, no")])
(define_mode_iterator MODE [BI QI HI SI DI SF DF XF TI])
+(define_mode_iterator MODE_FOR_CMP [BI SI DI SF DF XF (TF "TARGET_HPUX")])
(define_mode_iterator MODE_FOR_EXTEND [QI HI SI])
(define_mode_attr output_a [
@@ -5060,82 +5061,76 @@
;; ::
;; ::::::::::::::::::::
-(define_expand "cmpbi"
- [(set (cc0)
- (compare (match_operand:BI 0 "register_operand" "")
- (match_operand:BI 1 "const_int_operand" "")))]
+(define_expand "cbranchbi4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:BI 1 "register_operand" "")
+ (match_operand:BI 2 "const_int_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
-{
- ia64_compare_op0 = operands[0];
- ia64_compare_op1 = operands[1];
- DONE;
-})
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
-(define_expand "cmpsi"
- [(set (cc0)
- (compare (match_operand:SI 0 "gr_register_operand" "")
- (match_operand:SI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
+(define_expand "cbranchsi4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:SI 1 "gr_register_operand" "")
+ (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
-{
- ia64_compare_op0 = operands[0];
- ia64_compare_op1 = operands[1];
- DONE;
-})
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
-(define_expand "cmpdi"
- [(set (cc0)
- (compare (match_operand:DI 0 "gr_register_operand" "")
- (match_operand:DI 1 "gr_reg_or_8bit_and_adjusted_operand" "")))]
+(define_expand "cbranchdi4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:DI 1 "gr_register_operand" "")
+ (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
-{
- ia64_compare_op0 = operands[0];
- ia64_compare_op1 = operands[1];
- DONE;
-})
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
-(define_expand "cmpsf"
- [(set (cc0)
- (compare (match_operand:SF 0 "fr_reg_or_fp01_operand" "")
- (match_operand:SF 1 "fr_reg_or_fp01_operand" "")))]
+(define_expand "cbranchsf4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:SF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
-{
- ia64_compare_op0 = operands[0];
- ia64_compare_op1 = operands[1];
- DONE;
-})
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
-(define_expand "cmpdf"
- [(set (cc0)
- (compare (match_operand:DF 0 "fr_reg_or_fp01_operand" "")
- (match_operand:DF 1 "fr_reg_or_fp01_operand" "")))]
+(define_expand "cbranchdf4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:DF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
-{
- ia64_compare_op0 = operands[0];
- ia64_compare_op1 = operands[1];
- DONE;
-})
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
-(define_expand "cmpxf"
- [(set (cc0)
- (compare (match_operand:XF 0 "xfreg_or_fp01_operand" "")
- (match_operand:XF 1 "xfreg_or_fp01_operand" "")))]
+(define_expand "cbranchxf4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:XF 1 "xfreg_or_fp01_operand" "")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
""
-{
- ia64_compare_op0 = operands[0];
- ia64_compare_op1 = operands[1];
- DONE;
-})
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
-(define_expand "cmptf"
- [(set (cc0)
- (compare (match_operand:TF 0 "gr_register_operand" "")
- (match_operand:TF 1 "gr_register_operand" "")))]
+(define_expand "cbranchtf4"
+ [(set (pc)
+ (if_then_else (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:TF 1 "gr_register_operand" "")
+ (match_operand:TF 2 "gr_register_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+ (pc)))]
"TARGET_HPUX"
-{
- ia64_compare_op0 = operands[0];
- ia64_compare_op1 = operands[1];
- DONE;
-})
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
(define_insn "*cmpsi_normal"
[(set (match_operand:BI 0 "register_operand" "=c")
@@ -5234,102 +5229,6 @@
;; ::
;; ::::::::::::::::::::
-(define_expand "beq"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (EQ, VOIDmode);")
-
-(define_expand "bne"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (NE, VOIDmode);")
-
-(define_expand "blt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (LT, VOIDmode);")
-
-(define_expand "ble"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (LE, VOIDmode);")
-
-(define_expand "bgt"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (GT, VOIDmode);")
-
-(define_expand "bge"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (GE, VOIDmode);")
-
-(define_expand "bltu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (LTU, VOIDmode);")
-
-(define_expand "bleu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (LEU, VOIDmode);")
-
-(define_expand "bgtu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (GTU, VOIDmode);")
-
-(define_expand "bgeu"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (GEU, VOIDmode);")
-
-(define_expand "bunordered"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (UNORDERED, VOIDmode);")
-
-(define_expand "bordered"
- [(set (pc)
- (if_then_else (match_dup 1)
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "operands[1] = ia64_expand_compare (ORDERED, VOIDmode);")
-
(define_insn "*br_true"
[(set (pc)
(if_then_else (match_operator 0 "predicate_operator"
@@ -5395,65 +5294,61 @@
;; ::
;; ::::::::::::::::::::
-(define_expand "seq"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (EQ, DImode);")
-
-(define_expand "sne"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (NE, DImode);")
-
-(define_expand "slt"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (LT, DImode);")
-
-(define_expand "sle"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (LE, DImode);")
-
-(define_expand "sgt"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (GT, DImode);")
-
-(define_expand "sge"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (GE, DImode);")
-
-(define_expand "sltu"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (LTU, DImode);")
-
-(define_expand "sleu"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (LEU, DImode);")
-
-(define_expand "sgtu"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (GTU, DImode);")
-
-(define_expand "sgeu"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (GEU, DImode);")
-
-(define_expand "sunordered"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (UNORDERED, DImode);")
-
-(define_expand "sordered"
- [(set (match_operand:DI 0 "gr_register_operand" "") (match_dup 1))]
- ""
- "operands[1] = ia64_expand_compare (ORDERED, DImode);")
+(define_expand "cstorebi4"
+ [(set (match_operand:DI 0 "gr_register_operand" "")
+ (match_operator:DI 1 "ia64_cbranch_operator"
+ [(match_operand:BI 2 "register_operand" "")
+ (match_operand:BI 3 "const_int_operand" "")]))]
+ ""
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
+(define_expand "cstoresi4"
+ [(set (match_operand:DI 0 "gr_register_operand" "")
+ (match_operator:DI 1 "ia64_cbranch_operator"
+ [(match_operand:SI 2 "gr_register_operand" "")
+ (match_operand:SI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))]
+ ""
+ "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
+
+(define_expand "cstoredi4"
+ [(set (match_operand:DI 0 "gr_register_operand" "")
+ (match_operator:DI 1 "ia64_cbranch_operator"
+ [(match_operand:DI 2 "gr_register_operand" "")
+ (match_operand:DI 3 "gr_reg_or_8bit_and_adjusted_operand" "")]))]
+ ""
+ "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
+
+(define_expand "cstoresf4"
+ [(set (match_operand:DI 0 "gr_register_operand" "")
+ (match_operator:DI 1 "ia64_cbranch_operator"
+ [(match_operand:SF 2 "fr_reg_or_fp01_operand" "")
+ (match_operand:SF 3 "fr_reg_or_fp01_operand" "")]))]
+ ""
+ "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
+
+(define_expand "cstoredf4"
+ [(set (match_operand:DI 0 "gr_register_operand" "")
+ (match_operator:DI 1 "ia64_cbranch_operator"
+ [(match_operand:DF 2 "fr_reg_or_fp01_operand" "")
+ (match_operand:DF 3 "fr_reg_or_fp01_operand" "")]))]
+ ""
+ "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
+
+(define_expand "cstorexf4"
+ [(set (match_operand:DI 0 "gr_register_operand" "")
+ (match_operator:DI 1 "ia64_cbranch_operator"
+ [(match_operand:XF 2 "xfreg_or_fp01_operand" "")
+ (match_operand:XF 3 "xfreg_or_fp01_operand" "")]))]
+ ""
+ "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
+
+(define_expand "cstoretf4"
+ [(set (match_operand:DI 0 "gr_register_operand" "")
+ (match_operator:DI 1 "ia64_cbranch_operator"
+ [(match_operand:TF 2 "gr_register_operand" "")
+ (match_operand:TF 3 "gr_register_operand" "")]))]
+ "TARGET_HPUX"
+ "ia64_expand_compare (&operands[1], &operands[2], &operands[3]);")
;; Don't allow memory as destination here, because cmov/cmov/st is more
;; efficient than mov/mov/cst/cst.
@@ -6319,12 +6214,62 @@
"break %0"
[(set_attr "itanium_class" "chk_s_i")])
-(define_expand "conditional_trap"
- [(trap_if (match_operand 0 "" "") (match_operand 1 "" ""))]
- ""
-{
- operands[0] = ia64_expand_compare (GET_CODE (operands[0]), VOIDmode);
-})
+(define_expand "ctrapbi4"
+ [(trap_if (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:BI 1 "register_operand" "")
+ (match_operand:BI 2 "const_int_operand" "")])
+ (match_operand 3 "" ""))]
+ ""
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
+(define_expand "ctrapsi4"
+ [(trap_if (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:SI 1 "gr_register_operand" "")
+ (match_operand:SI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
+ (match_operand 3 "" ""))]
+ ""
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
+(define_expand "ctrapdi4"
+ [(trap_if (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:DI 1 "gr_register_operand" "")
+ (match_operand:DI 2 "gr_reg_or_8bit_and_adjusted_operand" "")])
+ (match_operand 3 "" ""))]
+ ""
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
+(define_expand "ctrapsf4"
+ [(trap_if (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:SF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:SF 2 "fr_reg_or_fp01_operand" "")])
+ (match_operand 3 "" ""))]
+ ""
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
+(define_expand "ctrapdf4"
+ [(trap_if (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:DF 1 "fr_reg_or_fp01_operand" "")
+ (match_operand:DF 2 "fr_reg_or_fp01_operand" "")])
+ (match_operand 3 "" ""))]
+ ""
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
+(define_expand "ctrapxf4"
+ [(trap_if (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:XF 1 "xfreg_or_fp01_operand" "")
+ (match_operand:XF 2 "xfreg_or_fp01_operand" "")])
+ (match_operand 3 "" ""))]
+ ""
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
+(define_expand "ctraptf4"
+ [(trap_if (match_operator 0 "ia64_cbranch_operator"
+ [(match_operand:TF 1 "gr_register_operand" "")
+ (match_operand:TF 2 "gr_register_operand" "")])
+ (match_operand 3 "" ""))]
+ "TARGET_HPUX"
+ "ia64_expand_compare (&operands[0], &operands[1], &operands[2]);")
+
(define_insn "*conditional_trap"
[(trap_if (match_operator 0 "predicate_operator"
Index: gcc/config/ia64/predicates.md
===================================================================
--- gcc/config/ia64/predicates.md (branch cond-optab)
+++ gcc/config/ia64/predicates.md (working copy)
@@ -536,6 +536,11 @@
(and (match_code "const_double,const_vector")
(match_test "op == CONST0_RTX (GET_MODE (op))"))))
+;; Return 1 if OP is a valid comparison operator for "cbranch" instructions.
+(define_predicate "ia64_cbranch_operator"
+ (ior (match_operand 0 "ordered_comparison_operator")
+ (match_code "ordered,unordered")))
+
;; True if this is a comparison operator, which accepts a normal 8-bit
;; signed immediate operand.
(define_predicate "normal_comparison_operator"