This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[cond-optab] Convert v850 to cbranchsi4/cstoresi4
- From: Paolo Bonzini <bonzini at gnu dot org>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 16 Mar 2009 15:12:03 +0100
- Subject: [cond-optab] Convert v850 to cbranchsi4/cstoresi4
Here is the conversion for a simple CC0 target, eliminating over 150
lines of code (also thanks to the non-usage of macros in the target).
Most other embedded targets should be as simple as this. I have also an
i386 conversion coming, showing that the plan is actually feasible. So
now, if people want to help, I can put the stuff on a branch.
Paolo
2009-03-16 Paolo Bonzini <bonzini@gnu.org>
* config/v850/v850.md (tstsi, cmpsi): Fold into...
(*cmpsi): ... this one.
(cbranchsi4, cstoresi4): New.
(bCC expanders): Delete.
(sCC insns): Fold into...
(*setcc): ... this one.
(casesi): Do not use gen_cmpsi and gen_bgtu.
Index: config/v850/v850.md
===================================================================
*** config/v850/v850.md (revision 144857)
--- config/v850/v850.md (working copy)
***************
*** 251,273 ****
(match_dup 2)))
(set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
! (define_insn "tstsi"
! [(set (cc0) (match_operand:SI 0 "register_operand" "r"))]
! ""
! "cmp %.,%0"
! [(set_attr "length" "2")
! (set_attr "cc" "set_znv")])
! (define_insn "cmpsi"
[(set (cc0)
! (compare (match_operand:SI 0 "register_operand" "r,r")
! (match_operand:SI 1 "reg_or_int5_operand" "r,J")))]
""
"@
cmp %1,%0
cmp %1,%0"
! [(set_attr "length" "2,2")
! (set_attr "cc" "compare")])
;; ----------------------------------------------------------------------
;; ADD INSTRUCTIONS
--- 251,289 ----
(match_dup 2)))
(set (match_dup 0) (ne:SI (cc0) (const_int 0)))])
! (define_expand "cbranchsi4"
! [(set (cc0)
! (compare (match_operand:SI 1 "register_operand" "")
! (match_operand:SI 2 "reg_or_int5_operand" "")))
! (set (pc)
! (if_then_else
! (match_operator 0 "comparison_operator" [(cc0)
! (const_int 0)])
! (label_ref (match_operand 3 "" ""))
! (pc)))]
! "")
! (define_expand "cstoresi4"
[(set (cc0)
! (compare (match_operand:SI 2 "register_operand" "")
! (match_operand:SI 3 "reg_or_int5_operand" "")))
! (set (match_operand:SI 0 "register_operand")
! (match_operator:SI 1 "comparison_operator" [(cc0)
! (const_int 0)]))]
! "")
!
! (define_insn "*cmpsi"
! [(set (cc0)
! (compare (match_operand:SI 0 "register_operand" "r,r,r")
! (match_operand:SI 1 "reg_or_int5_operand" "r,I,J")))]
""
"@
cmp %1,%0
+ cmp %.,%0
cmp %1,%0"
! [(set_attr "length" "2,2,2")
! (set_attr "cc" "compare,set_znv,compare")])
!
;; ----------------------------------------------------------------------
;; ADD INSTRUCTIONS
***************
*** 688,797 ****
;; Scc INSTRUCTIONS
;; -----------------------------------------------------------------
! (define_insn "sle"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (le:SI (cc0) (const_int 0)))]
! ""
! "*
! {
! if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
! return 0;
!
! return \"setf le,%0\";
! }"
! [(set_attr "length" "4")
! (set_attr "cc" "none_0hit")])
!
! (define_insn "sleu"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (leu:SI (cc0) (const_int 0)))]
! ""
! "setf nh,%0"
! [(set_attr "length" "4")
! (set_attr "cc" "none_0hit")])
!
! (define_insn "sge"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (ge:SI (cc0) (const_int 0)))]
! ""
! "*
! {
! if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
! return 0;
!
! return \"setf ge,%0\";
! }"
! [(set_attr "length" "4")
! (set_attr "cc" "none_0hit")])
!
! (define_insn "sgeu"
[(set (match_operand:SI 0 "register_operand" "=r")
! (geu:SI (cc0) (const_int 0)))]
! ""
! "setf nl,%0"
! [(set_attr "length" "4")
! (set_attr "cc" "none_0hit")])
!
! (define_insn "slt"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (lt:SI (cc0) (const_int 0)))]
! ""
! "*
! {
! if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
! return 0;
!
! return \"setf lt,%0\";
! }"
! [(set_attr "length" "4")
! (set_attr "cc" "none_0hit")])
!
! (define_insn "sltu"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (ltu:SI (cc0) (const_int 0)))]
! ""
! "setf l,%0"
! [(set_attr "length" "4")
! (set_attr "cc" "none_0hit")])
!
! (define_insn "sgt"
! [(set (match_operand:SI 0 "register_operand" "=r")
! (gt:SI (cc0) (const_int 0)))]
""
"*
{
! if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0)
return 0;
! return \"setf gt,%0\";
}"
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")])
- (define_insn "sgtu"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (gtu:SI (cc0) (const_int 0)))]
- ""
- "setf h,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
-
- (define_insn "seq"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (eq:SI (cc0) (const_int 0)))]
- ""
- "setf z,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
-
- (define_insn "sne"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (ne:SI (cc0) (const_int 0)))]
- ""
- "setf nz,%0"
- [(set_attr "length" "4")
- (set_attr "cc" "none_0hit")])
-
;; ----------------------------------------------------------------------
;; CONDITIONAL MOVE INSTRUCTIONS
;; ----------------------------------------------------------------------
--- 704,728 ----
;; Scc INSTRUCTIONS
;; -----------------------------------------------------------------
! (define_insn "*setcc"
[(set (match_operand:SI 0 "register_operand" "=r")
! (match_operator:SI 1 "comparison_operator"
! [(cc0) (const_int 0)]))]
""
"*
{
! if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0
! && (GET_CODE (operands[1]) == GT
! || GET_CODE (operands[1]) == GE
! || GET_CODE (operands[1]) == LE
! || GET_CODE (operands[1]) == LT))
return 0;
! return \"setf %c1,%0\";
}"
[(set_attr "length" "4")
(set_attr "cc" "none_0hit")])
;; ----------------------------------------------------------------------
;; CONDITIONAL MOVE INSTRUCTIONS
;; ----------------------------------------------------------------------
***************
*** 1037,1132 ****
;; Conditional jump instructions
- (define_expand "ble"
- [(set (pc)
- (if_then_else (le (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "bleu"
- [(set (pc)
- (if_then_else (leu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "bge"
- [(set (pc)
- (if_then_else (ge (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "bgeu"
- [(set (pc)
- (if_then_else (geu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "blt"
- [(set (pc)
- (if_then_else (lt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "bltu"
- [(set (pc)
- (if_then_else (ltu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "bgt"
- [(set (pc)
- (if_then_else (gt (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "bgtu"
- [(set (pc)
- (if_then_else (gtu (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "beq"
- [(set (pc)
- (if_then_else (eq (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
- (define_expand "bne"
- [(set (pc)
- (if_then_else (ne (cc0)
- (const_int 0))
- (label_ref (match_operand 0 "" ""))
- (pc)))]
- ""
- "")
-
(define_insn "*branch_normal"
[(set (pc)
(if_then_else (match_operator 1 "comparison_operator"
--- 968,973 ----
***************
*** 1241,1254 ****
{
rtx reg = gen_reg_rtx (SImode);
rtx tableaddress = gen_reg_rtx (SImode);
rtx mem;
/* Subtract the lower bound from the index. */
emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
! /* Compare the result against the number of table entries. */
! emit_insn (gen_cmpsi (reg, operands[2]));
! /* Branch to the default label if out of range of the table. */
! emit_jump_insn (gen_bgtu (operands[4]));
/* Shift index for the table array access. */
emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));
--- 1082,1097 ----
{
rtx reg = gen_reg_rtx (SImode);
rtx tableaddress = gen_reg_rtx (SImode);
+ rtx test;
rtx mem;
/* Subtract the lower bound from the index. */
emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
!
! /* Compare the result against the number of table entries;
! branch to the default label if out of range of the table. */
! test = gen_rtx_fmt_ee (GTU, VOIDmode, reg, operands[2]);
! emit_jump_insn (gen_cbranchsi4 (test, reg, operands[2], operands[4]));
/* Shift index for the table array access. */
emit_insn (gen_ashlsi3 (reg, reg, GEN_INT (TARGET_BIG_SWITCH ? 2 : 1)));