This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [PATCH] MIPS function attributes for interrupt handlers
On Fri, 27 Feb 2009, Fu, Chao-Ying wrote:
> > Please note that "eret" is not supported for -march=mips1 and
> > -march=mips2 in GAS as those ISAs did not have this instrution ("rfe" in
> > the delay slot of a "jr" was used instead). While, if I understand
> > correctly, the interrupt function attribute makes sense for the EIC mode
> > only, I suggest that you make sure the compiler does not produce code GAS
> > will refuse to swallow for older ISAs. Perhaps the attribute should only
> > be supported for ISAs which can actually run the resulting code
> > ("-march=mips32" and above?).
>
> It can be used for the original mode (single,ilp0.. ilp7) and the EIC
> mode.
>
> People just need to put GCC-generated handlers to the address they want
> in the linker script, and provide some bootup code.
Hmm, I thought the shadow register sets could only be switched
automatically with the EIC mode. I have checked the ISA doc now to be
proved I was slightly confused -- the R2 ISA retrofitted the SRS switching
into the older concept of the use of a dedicated exception vector (as
provided by cp0.cause.iv) for the interrupt exception.
All is a new MIPS32r2/MIPS64r2 addition anyway. With older processors
you have to perform stack switching in software and then save/restore
registers on the interrupt stack and I think that's too system-specific to
be doable from the compiler in a generic way.
> Maybe we just emit "jr" and "ref", when mips1 or mips2 is used to compile
> code.
IMO it does not make sense to support it in any way except from making a
small amount of effort to make sure such configurations do not make the
tools behave inconsistently. There is no MIPS I or II processor that
would support the SRS so the interrupt handler won't ever run on one.
Maciej