This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
RE: PATCH: Update classification of aggregates with __m256 ([AVX]: Update x86-64 psABI for aggregates with __m256)
- From: "Jagasia, Harsha" <harsha dot jagasia at amd dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>, "Uros Bizjak" <ubizjak at gmail dot com>, "Jan Hubicka" <jh at suse dot cz>
- Cc: <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 11 Feb 2009 14:42:54 -0600
- Subject: RE: PATCH: Update classification of aggregates with __m256 ([AVX]: Update x86-64 psABI for aggregates with __m256)
>On Wed, Feb 11, 2009 at 10:16 AM, Harsha Jagasia
<harsha.jagasia@amd.com> wrote:
>>> -------------
>>> @@ -5331,14 +5352,22 @@ construct_container (enum machine_mode m
>>> break;
>>> case X86_64_SSE_CLASS:
>>> if (i < n - 1 && regclass[i + 1] == X86_64_SSEUP_CLASS)
>>> - tmpmode = TImode;
>>> + {
>>> + if (regclass[i + 2] == X86_64_SSEUP_CLASS
>>> + || regclass[i + 3] == X86_64_SSEUP_CLASS)
>>> + tmpmode = OImode;
>>> + else
>>> + tmpmode = TImode;
>>> + }
>>>
>>
>>
>> I would think a check for n is needed here. If n is 2, regclass[i +
2] and regclass[i + 3] would
>not be valid, right?
>>
>
>This patch rewrites processing BLKmode with X86_64_SSE_CLASS.
This looks fine to me.
>OK for trunk if there is no regression on Linux/x86-64?
>
>Thanks.
>
>
>--
>H.J.
>---
>2009-02-11 H.J. Lu <hongjiu.lu@intel.com>
>
> * config/i386/i386.c (construct_container): Rewrite processing
> BLKmode with X86_64_SSE_CLASS.