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[PATCH] s390: z10 scheduler fixes part 1/4
- From: Wolfgang Gellerich <gelleric at linux dot vnet dot ibm dot com>
- To: GCC-Patches <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 28 Jan 2009 16:42:08 +0100
- Subject: [PATCH] s390: z10 scheduler fixes part 1/4
This is the first from a total of 4 patches that fix the declaration of
z10 pipeline properties of instructions declared in s390.md, and some
minor mistakes in comments I stumbled over. The fixes come from a code
review and from checking the differences provided by an updated version
of the respective z10 design document.
All four patches are ok with respect to bootstrapping and regression
testing. For patches 1, 2, and 3 we also measured the impact on
performance. The overall result is a slight improvement.
This first patch contains fixes concerning the z10prop attribute.
Regards, Wolfgang
--
---
Dr. Wolfgang Gellerich
IBM Deutschland Entwicklung GmbH
Schönaicher Strasse 220
71032 Böblingen, Germany
Tel. +49 / 7031 / 162598
gellerich@de.ibm.com
=======================
IBM Deutschland Entwicklung GmbH
Vorsitzender des Aufsichtsrats: Martin Jetter
Geschäftsführung: Erich Baier
Sitz der Gesellschaft: Böblingen
Registergericht: Amtsgericht Stuttgart, HRB 243294
Changelog:
2009-01-28 Wolfgang Gellerich <gellerich@de.ibm.com>
* config/s390/s390.md (*tmsi_reg): Fixed z10prop attribute.
(*tm<mode>_full): Fixed z10prop attribute.
(*tst<mode>_extimm): Fixed z10prop attribute.
(*tst<mode>_cconly_extimm): Fixed z10prop attribute.
(*tstqiCCT_cconly): Fixed z10prop attribute.
(*cmpsi_ccu_zerohi_rlsi): Fixed z10prop attribute.
(*movsi_larl): Fixed z10prop attribute.
(*movsi_zarch): Fixed z10prop attribute.
(*movsi_eas): Fixed z10prop attribute.
(*movhi): Fixed z10prop attribute.
(*movqi): Fixed z10prop attribute.
(*movstrictqi): Fixed z10prop attribute.
(*mov<mode>): Fixed z10prop attribute.
(*movcc): Fixed z10prop attribute.
(*sethighpartdi_64): Fixed z10prop attribute.
(*zero_extendhi<mode>2_z10): Fixed z10prop attribute.
(*negdi2_sign_cc): Fixed z10prop attribute.
(*negdi2_sign): Fixed z10prop attribute.
(*absdi2_sign_cc): Fixed z10prop attribute.
(*absdi2_sign): Fixed z10prop attribute.
(*negabsdi2_sign_cc): Fixed z10prop attribute.
(*negabsdi2_sign): Fixed z10prop attribute.
(*cmp_and_trap_signed_int<mode>): Fixed z10prop attribute.
(*cmp_and_trap_unsigned_int<mode>): Fixed z10prop attribute.
(doloop_si64): Fixed z10prop attribute.
(doloop_si31): Fixed z10prop attribute.
(doloop_long): Fixed z10prop attribute.
(indirect_jump): Fixed z10prop attribute.
(nop): Fixed z10prop attribute.
(main_base_64): Fixed z10prop attribute.
(reload_base_64): Fixed z10prop attribute.
Index: gcc/config/s390/s390.md
===================================================================
*** gcc/config/s390/s390.md.orig 2009-01-12 16:38:49.000000000 +0100
--- gcc/config/s390/s390.md 2009-01-13 15:36:53.000000000 +0100
***************
*** 558,564 ****
"@
tmh\t%0,%i1
tml\t%0,%i1"
! [(set_attr "op_type" "RI")])
(define_insn "*tm<mode>_full"
[(set (reg CC_REGNUM)
--- 558,565 ----
"@
tmh\t%0,%i1
tml\t%0,%i1"
! [(set_attr "op_type" "RI")
! (set_attr "z10prop" "z10_super,z10_super")])
(define_insn "*tm<mode>_full"
[(set (reg CC_REGNUM)
***************
*** 566,572 ****
(match_operand:HQI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
"tml\t%0,<max_uint>"
! [(set_attr "op_type" "RI")])
;
--- 567,574 ----
(match_operand:HQI 1 "immediate_operand" "n")))]
"s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))"
"tml\t%0,<max_uint>"
! [(set_attr "op_type" "RI")
! (set_attr "z10prop" "z10_super")])
;
***************
*** 604,610 ****
lt<g>r\t%2,%0
lt<g>\t%2,%0"
[(set_attr "op_type" "RR<E>,RXY")
! (set_attr "z10prop" "z10_fr_E1,z10_fr_A3") ])
; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_cconly_extimm"
--- 606,612 ----
lt<g>r\t%2,%0
lt<g>\t%2,%0"
[(set_attr "op_type" "RR<E>,RXY")
! (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ])
; ltr, lt, ltgr, ltg
(define_insn "*tst<mode>_cconly_extimm"
***************
*** 617,623 ****
lt<g>r\t%0,%0
lt<g>\t%2,%0"
[(set_attr "op_type" "RR<E>,RXY")
! (set_attr "z10prop" "z10_fr_E1,z10_fr_A3")])
(define_insn "*tstdi"
[(set (reg CC_REGNUM)
--- 619,625 ----
lt<g>r\t%0,%0
lt<g>\t%2,%0"
[(set_attr "op_type" "RR<E>,RXY")
! (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")])
(define_insn "*tstdi"
[(set (reg CC_REGNUM)
***************
*** 715,721 ****
cliy\t%S0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")
! (set_attr "z10prop" "z10_super,z10_super,*")])
(define_insn "*tst<mode>"
[(set (reg CC_REGNUM)
--- 717,723 ----
cliy\t%S0,0
tml\t%0,255"
[(set_attr "op_type" "SI,SIY,RI")
! (set_attr "z10prop" "z10_super,z10_super,z10_super")])
(define_insn "*tst<mode>"
[(set (reg CC_REGNUM)
***************
*** 856,862 ****
"s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
"clhrl\t%0,%1"
[(set_attr "op_type" "RIL")
! (set_attr "type" "larl")])
; clhrl, clghrl
(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
--- 858,865 ----
"s390_match_ccmode(insn, CCURmode) && TARGET_Z10"
"clhrl\t%0,%1"
[(set_attr "op_type" "RIL")
! (set_attr "type" "larl")
! (set_attr "z10prop" "z10_super")])
; clhrl, clghrl
(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi"
***************
*** 1527,1533 ****
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
! (set_attr "z10prop" "z10_super_A1")])
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
--- 1530,1536 ----
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
! (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "*movsi_zarch"
[(set (match_operand:SI 0 "nonimmediate_operand"
***************
*** 1593,1599 ****
z10_fr_E1,
z10_fwd_A3,
z10_fwd_A3,
! z10_super,
z10_rec,
*,
*,
--- 1596,1602 ----
z10_fr_E1,
z10_fwd_A3,
z10_fwd_A3,
! z10_rec,
z10_rec,
*,
*,
***************
*** 1628,1634 ****
(set_attr "z10prop" "z10_fwd_A1,
z10_fr_E1,
z10_fwd_A3,
! z10_super,
*,
*,
*,
--- 1631,1637 ----
(set_attr "z10prop" "z10_fwd_A1,
z10_fr_E1,
z10_fwd_A3,
! z10_rec,
*,
*,
*,
***************
*** 1766,1772 ****
z10_super_E1,
z10_super_E1,
z10_super_E1,
! z10_super,
z10_rec,
z10_rec,
z10_super")])
--- 1769,1775 ----
z10_super_E1,
z10_super_E1,
z10_super_E1,
! z10_rec,
z10_rec,
z10_rec,
z10_super")])
***************
*** 1822,1828 ****
z10_fwd_A1,
z10_super_E1,
z10_super_E1,
! z10_super,
z10_rec,
z10_super,
z10_super")])
--- 1825,1831 ----
z10_fwd_A1,
z10_super_E1,
z10_super_E1,
! z10_rec,
z10_rec,
z10_super,
z10_super")])
***************
*** 1849,1855 ****
ic\t%0,%1
icy\t%0,%1"
[(set_attr "op_type" "RX,RXY")
! (set_attr "z10prop" "z10_super_E1,z10_super")])
;
; movstricthi instruction pattern(s).
--- 1852,1858 ----
ic\t%0,%1
icy\t%0,%1"
[(set_attr "op_type" "RX,RXY")
! (set_attr "z10prop" "z10_super_E1,z10_super_E1")])
;
; movstricthi instruction pattern(s).
***************
*** 2167,2173 ****
z10_fr_E1,
z10_fwd_A3,
z10_fwd_A3,
! z10_super,
z10_rec")])
;
--- 2170,2176 ----
z10_fr_E1,
z10_fwd_A3,
z10_fwd_A3,
! z10_rec,
z10_rec")])
;
***************
*** 2188,2194 ****
ly\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
(set_attr "type" "lr,*,*,store,store,load,load")
! (set_attr "z10prop" "z10_fr_E1,*,*,z10_super,z10_rec,z10_fwd_A3,z10_fwd_A3")])
;
; Block move (MVC) patterns.
--- 2191,2197 ----
ly\t%1,%0"
[(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY")
(set_attr "type" "lr,*,*,store,store,load,load")
! (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_rec,z10_rec,z10_fwd_A3,z10_fwd_A3")])
;
; Block move (MVC) patterns.
***************
*** 3153,3159 ****
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"icmh\t%0,%2,%S1"
! [(set_attr "op_type" "RSY")])
(define_insn "*sethighpartdi_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
--- 3156,3163 ----
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"icmh\t%0,%2,%S1"
! [(set_attr "op_type" "RSY")
! (set_attr "z10prop" "z10_super")])
(define_insn "*sethighpartdi_31"
[(set (match_operand:DI 0 "register_operand" "=d,d")
***************
*** 3696,3702 ****
[(set_attr "op_type" "RXY,RRE,RIL")
(set_attr "type" "*,*,larl")
(set_attr "cpu_facility" "*,*,z10")
! (set_attr "z10prop" "z10_fwd_A3")])
; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
--- 3700,3706 ----
[(set_attr "op_type" "RXY,RRE,RIL")
(set_attr "type" "*,*,larl")
(set_attr "cpu_facility" "*,*,z10")
! (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")])
; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc
(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm"
***************
*** 6630,6636 ****
(neg:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
! [(set_attr "op_type" "RRE")])
(define_insn "*negdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 6634,6641 ----
(neg:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lcgfr\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "z10prop" "z10_c")])
(define_insn "*negdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 6638,6644 ****
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lcgfr\t%0,%1"
! [(set_attr "op_type" "RRE")])
; lcr, lcgr
(define_insn "*neg<mode>2_cc"
--- 6643,6650 ----
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lcgfr\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "z10prop" "z10_c")])
; lcr, lcgr
(define_insn "*neg<mode>2_cc"
***************
*** 6774,6780 ****
(abs:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
! [(set_attr "op_type" "RRE")])
(define_insn "*absdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 6780,6787 ----
(abs:DI (sign_extend:DI (match_dup 1))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lpgfr\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "z10prop" "z10_c")])
(define_insn "*absdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 6782,6788 ****
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lpgfr\t%0,%1"
! [(set_attr "op_type" "RRE")])
; lpr, lpgr
(define_insn "*abs<mode>2_cc"
--- 6789,6796 ----
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lpgfr\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "z10prop" "z10_c")])
; lpr, lpgr
(define_insn "*abs<mode>2_cc"
***************
*** 6890,6896 ****
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
! [(set_attr "op_type" "RRE")])
(define_insn "*negabsdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
--- 6898,6905 ----
(neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))]
"TARGET_64BIT && s390_match_ccmode (insn, CCAmode)"
"lngfr\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "z10prop" "z10_c")])
(define_insn "*negabsdi2_sign"
[(set (match_operand:DI 0 "register_operand" "=d")
***************
*** 6899,6905 ****
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lngfr\t%0,%1"
! [(set_attr "op_type" "RRE")])
; lnr, lngr
(define_insn "*negabs<mode>2_cc"
--- 6908,6915 ----
(clobber (reg:CC CC_REGNUM))]
"TARGET_64BIT"
"lngfr\t%0,%1"
! [(set_attr "op_type" "RRE")
! (set_attr "z10prop" "z10_c")])
; lnr, lngr
(define_insn "*negabs<mode>2_cc"
***************
*** 7516,7522 ****
c<g>it%C0\t%1,%h2"
[(set_attr "op_type" "RRF,RIE")
(set_attr "type" "branch")
! (set_attr "z10prop" "z10_c,*")])
; clrt, clgrt, clfit, clgit
(define_insn "*cmp_and_trap_unsigned_int<mode>"
--- 7526,7532 ----
c<g>it%C0\t%1,%h2"
[(set_attr "op_type" "RRF,RIE")
(set_attr "type" "branch")
! (set_attr "z10prop" "z10_super_c,z10_super")])
; clrt, clgrt, clfit, clgit
(define_insn "*cmp_and_trap_unsigned_int<mode>"
***************
*** 7530,7536 ****
cl<gf>it%C0\t%1,%x2"
[(set_attr "op_type" "RRF,RIE")
(set_attr "type" "branch")
! (set_attr "z10prop" "z10_c,*")])
;;
;;- Loop instructions.
--- 7540,7546 ----
cl<gf>it%C0\t%1,%x2"
[(set_attr "op_type" "RRF,RIE")
(set_attr "type" "branch")
! (set_attr "z10prop" "z10_super_c,z10_super")])
;;
;;- Loop instructions.
***************
*** 7594,7600 ****
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
! (set_attr "z10prop" "z10_super")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
--- 7604,7610 ----
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
! (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
***************
*** 7636,7642 ****
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
! (set_attr "z10prop" "z10_super")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
--- 7646,7652 ----
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
! (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (eq (symbol_ref "flag_pic") (const_int 0))
***************
*** 7667,7673 ****
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
! (set_attr "atype" "agen")])
(define_insn_and_split "doloop_di"
[(set (pc)
--- 7677,7684 ----
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
! (set_attr "atype" "agen")
! (set_attr "z10prop" "z10_cobra")])
(define_insn_and_split "doloop_di"
[(set (pc)
***************
*** 7705,7711 ****
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
! (set_attr "z10prop" "z10_super")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
--- 7716,7722 ----
[(set_attr "op_type" "RI")
; Strictly speaking, the z10 properties are valid for brct only, however, it does not
; hurt us in the (rare) case of ahi.
! (set_attr "z10prop" "z10_super_E1")
(set_attr "type" "branch")
(set (attr "length")
(if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000))
***************
*** 7772,7779 ****
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
! (set_attr "atype" "agen")
! (set_attr "z10prop" "z10_super")])
;
; casesi instruction pattern(s).
--- 7783,7789 ----
(if_then_else (match_operand 0 "register_operand" "")
(const_string "RR") (const_string "RX")))
(set_attr "type" "branch")
! (set_attr "atype" "agen")])
;
; casesi instruction pattern(s).
***************
*** 8468,8474 ****
[(const_int 0)]
""
"lr\t0,0"
! [(set_attr "op_type" "RR")])
(define_insn "nop1"
[(const_int 1)]
--- 8478,8485 ----
[(const_int 0)]
""
"lr\t0,0"
! [(set_attr "op_type" "RR")
! (set_attr "z10prop" "z10_fr_E1")])
(define_insn "nop1"
[(const_int 1)]
***************
*** 8536,8542 ****
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
! (set_attr "z10prop" "z10_super_A1")])
(define_insn "main_pool"
[(set (match_operand 0 "register_operand" "=a")
--- 8547,8553 ----
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
! (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "main_pool"
[(set (match_operand 0 "register_operand" "=a")
***************
*** 8564,8570 ****
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
! (set_attr "z10prop" "z10_super_A1")])
(define_insn "pool"
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]
--- 8575,8581 ----
"larl\t%0,%1"
[(set_attr "op_type" "RIL")
(set_attr "type" "larl")
! (set_attr "z10prop" "z10_fwd_A1")])
(define_insn "pool"
[(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)]