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[m32c] minor fixes
- From: DJ Delorie <dj at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 26 Nov 2008 22:08:57 -0500
- Subject: [m32c] minor fixes
A couple of minor fixes and tweaks. Committed.
2008-11-26 DJ Delorie <dj@redhat.com>
* config/m32c/mov.md ("extendhipsi2"): New.
* config/m32c/bitops.md (bset_qi): Add memsym_operand predicate.
* config/m32c/bitops.md (andhi3_24, iorhi3_24): Don't prefer HL class.
* config/m32c/mov.md (zero_extendqihi2): Likewise.
Index: config/m32c/bitops.md
===================================================================
--- config/m32c/bitops.md (revision 142236)
+++ config/m32c/bitops.md (working copy)
@@ -40,13 +40,13 @@
;; First off, all the ways we can set one bit, other than plain IOR.
(define_insn "bset_qi"
[(set (match_operand:QI 0 "memsym_operand" "+Si")
(ior:QI (subreg:QI (ashift:HI (const_int 1)
(subreg:QI (match_operand:HI 1 "a_qi_operand" "Raa") 0)) 0)
- (match_operand:QI 2 "" "0")))]
+ (match_operand:QI 2 "memsym_operand" "0")))]
"TARGET_A16"
"bset\t%0[%1]"
[(set_attr "flags" "n")]
)
(define_insn "bset_hi"
@@ -187,13 +187,13 @@
and.b\t%x2,%0
and.b\t%x2,%0"
[(set_attr "flags" "n,n,sz,sz,sz,sz")]
)
(define_insn "andhi3_24"
- [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,??Rmm,RhiSd,??Rmm")
+ [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,??Rmm,RhiSd,??Rmm")
(and:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
(match_operand:HI 2 "mrai_operand" "ImB,Imw,ImB,Imw,iRhiSd,?Rmm,?Rmm,iRhiSd")))]
"TARGET_A24"
"@
bclr\t%B2,%0
bclr\t%B2-8,1+%0
@@ -220,13 +220,13 @@
or.b\t%x2,%0
or.b\t%x2,%0"
[(set_attr "flags" "n,sz,sz,sz,sz")]
)
(define_insn "iorhi3_24"
- [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,Rqi,Rqi,RhiSd,RhiSd,??Rmm,??Rmm")
+ [(set (match_operand:HI 0 "mra_operand" "=Sd,Sd,?Rhl,?Rhl,RhiSd,RhiSd,??Rmm,??Rmm")
(ior:HI (match_operand:HI 1 "mra_operand" "%0,0,0,0,0,0,0,0")
(match_operand:HI 2 "mrai_operand" "Ilb,Ilw,Ilb,Ilw,iRhiSd,?Rmm,iRhiSd,?Rmm")))]
"TARGET_A24"
"@
bset\t%B2,%0
bset\t%B2-8,1+%0
Index: config/m32c/mov.md
===================================================================
--- config/m32c/mov.md (revision 142236)
+++ config/m32c/mov.md (working copy)
@@ -335,12 +335,22 @@
"*
if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
[(set_attr "flags" "x")]
)
+(define_insn "extendhipsi2"
+ [(set (match_operand:PSI 0 "register_operand" "=R03")
+ (sign_extend:PSI (match_operand:HI 1 "register_operand" "0")))]
+ ""
+ "*
+ if (REGNO(operands[0]) == 0) return \"exts.w\t%1\";
+ else return \"mov.w r1,r3 | sha.w #-8,r3 | sha.w #-7,r3\";"
+ [(set_attr "flags" "x")]
+ )
+
(define_insn "extendpsisi2"
[(set (match_operand:SI 0 "mr_operand" "=R03Sd*Rmm")
(sign_extend:SI (match_operand:PSI 1 "mr_operand" "0")))]
""
"; expand psi %1 to si %0"
[(set_attr "flags" "n")]
@@ -368,13 +378,13 @@
""
"mov.w\t#0,%H0"
[(set_attr "flags" "x")]
)
(define_insn "zero_extendqihi2"
- [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=Rhl,RhiSd*Rmm")
+ [(set (match_operand:HI 0 "m32c_nonimmediate_operand" "=?Rhl,RhiSd*Rmm")
(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,0")))]
""
"@
mov.b\t#0,%H0
and.w\t#255,%0"
[(set_attr "flags" "x,x")]