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[PATCH, mips]: Fix PR 37362: [4.4 Regression] Bootstrap broken on mipsisa64r2-linux-gcc
- From: Uros Bizjak <ubizjak at gmail dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 18 Nov 2008 22:13:08 +0100
- Subject: [PATCH, mips]: Fix PR 37362: [4.4 Regression] Bootstrap broken on mipsisa64r2-linux-gcc
Hello!
Attached patch fixes PR 37362. The problem was due to postreload TFmode
splitter that generated mthc1 and mfhc1 insn with wrong input operand types.
2008-11-18 Uros Bizjak <ubizjak@gmail.com>
PR target/37362
* config/mips/mips.md (move_doubleword_fpr<mode>): Check that "high"
is a register or zero operand in the correct mode before generating
mtch1 insn or a register operand in the correct mode before generating
mfch1 insn.
(mtch1<mode>): Correct operand 1 predicate to reg_or_0_operand.
testsuite/ChangeLog:
2008-11-18 Uros Bizjak <ubizjak@gmail.com>
PR target/37362
* gcc.target/mips/pr37362.c: New test.
Patch was tested by Nebu Philips [1], [2].
[1] http://gcc.gnu.org/ml/gcc-bugs/2008-11/msg01507.html
[2] http://gcc.gnu.org/bugzilla/show_bug.cgi?id=37362
Uros.
Index: config/mips/mips.md
===================================================================
--- config/mips/mips.md (revision 141944)
+++ config/mips/mips.md (working copy)
@@ -4527,7 +4527,7 @@
rtx low = mips_subword (operands[1], 0);
rtx high = mips_subword (operands[1], 1);
emit_insn (gen_load_low<mode> (operands[0], low));
- if (ISA_HAS_MXHC1)
+ if (ISA_HAS_MXHC1 && reg_or_0_operand (high, <HALFMODE>mode))
emit_insn (gen_mthc1<mode> (operands[0], high, operands[0]));
else
emit_insn (gen_load_high<mode> (operands[0], high, operands[0]));
@@ -4537,7 +4537,7 @@
rtx low = mips_subword (operands[0], 0);
rtx high = mips_subword (operands[0], 1);
emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx));
- if (ISA_HAS_MXHC1)
+ if (ISA_HAS_MXHC1 && register_operand (high, <HALFMODE>mode))
emit_insn (gen_mfhc1<mode> (high, operands[1]));
else
emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx));
@@ -4592,7 +4592,7 @@
;; value in the low word.
(define_insn "mthc1<mode>"
[(set (match_operand:SPLITF 0 "register_operand" "=f")
- (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ")
+ (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ")
(match_operand:SPLITF 2 "register_operand" "0")]
UNSPEC_MTHC1))]
"TARGET_HARD_FLOAT && ISA_HAS_MXHC1"
Index: testsuite/gcc.target/mips/pr37362.c
===================================================================
--- testsuite/gcc.target/mips/pr37362.c (revision 0)
+++ testsuite/gcc.target/mips/pr37362.c (revision 0)
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-march=mips64r2" } */
+
+typedef float TFtype __attribute__((mode(TF)));
+
+TFtype
+__powitf (TFtype x, int m)
+{
+ unsigned int n = m < 0 ? -m : m;
+ TFtype y = n % 2 ? x : 1;
+ while (n >>= 1)
+ {
+ x = x * x;
+ if (n % 2)
+ y = y * x;
+ }
+ return m < 0 ? 1/y : y;
+}
+