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Re: PATCH: Separate processor model from ix86_tune
- From: Michael Meissner <meissner at linux dot vnet dot ibm dot com>
- To: "H.J. Lu" <hjl dot tools at gmail dot com>
- Cc: Uros Bizjak <ubizjak at gmail dot com>, David Edelsohn <dje dot gcc at gmail dot com>, Jan Hubicka <jh at suse dot cz>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 7 Oct 2008 12:41:06 -0400
- Subject: Re: PATCH: Separate processor model from ix86_tune
- References: <303e1d290809251841y74e46103h43ad09cdb02a7c0e@mail.gmail.com> <6dc9ffc80809251937l6d0b186embef7e0e5b0d04d22@mail.gmail.com> <20080926141849.GA26296@caradoc.them.org> <6dc9ffc80809290943y5612bcb1g6b5efee7f4cd605a@mail.gmail.com> <6dc9ffc80810061053h418eb050g65069530f3f44ad@mail.gmail.com> <48EA7D4B.8010309@gmail.com> <6dc9ffc80810070705j19413a0al2ba6588badda68bc@mail.gmail.com>
On Tue, Oct 07, 2008 at 07:05:23AM -0700, H.J. Lu wrote:
> K8 and generic64 aren't identical:
>
> (define_insn_reservation "athlon_movlpd_load_k8" 2
> (and (eq_attr "cpu" "k8")
> (and (eq_attr "type" "ssemov")
> (match_operand:DF 1 "memory_operand" "")))
> "athlon-direct,athlon-fploadk8,athlon-fstore")
> (define_insn_reservation "athlon_movsd_load_generic64" 2
> (and (eq_attr "cpu" "generic64")
> (and (eq_attr "type" "ssemov")
> (match_operand:DF 1 "memory_operand" "")))
>
> "athlon-double,athlon-fploadk8,(athlon-fstore+athlon-fmul)")
Yes, and in the future I would expect generic64 to be more tuned to the current
shipping Intel and AMD chipsets (i.e. barcelona in the case of AMD).
--
Michael Meissner, IBM
4 Technology Place Drive, MS 2203A, Westford, MA, 01886, USA
meissner@linux.vnet.ibm.com