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Re: [PATCH, MIPS] Merge mul*3_mul3 patterns
- From: Adam Nemet <anemet at caviumnetworks dot com>
- To: Richard Sandiford <rdsandiford at googlemail dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Mon, 6 Oct 2008 17:34:48 -0700
- Subject: Re: [PATCH, MIPS] Merge mul*3_mul3 patterns
- References: <18655.13396.169185.75808@foo.home> <8763ocufl9.fsf@firetop.home>
Richard Sandiford writes:
> Adam Nemet <anemet@caviumnetworks.com> writes:
> > * config/mips/mips.md (mulsi3_mul3, muldi3_mul3): Merge these ...
> > (mul<mode>3_mul3): ... into this new template.
> >
> > testsuite/
> > * testsuite/gcc.target/mips/r3900-mult.c: New test.
>
> OK, thanks, but rather than adding -mgp32 to this test's dg-mipst-options,
> please add:
>
> -march=r3900 -
>
> to the "set mips_new_gp 32" switch statement in mips.exp:dg-mips-options.
> Preapproved with that change.
Thanks, I made that change. This is what I've checked in as r140922.
Adam
2008-10-06 Adam Nemet <anemet@caviumnetworks.com>
* config/mips/mips.md (mulsi3_mul3, muldi3_mul3): Merge these ...
(mul<mode>3_mul3): ... into this new template.
testsuite/
2008-10-06 Adam Nemet <anemet@caviumnetworks.com>
* gcc.target/mips/mips.exp (dg-mips-options): Set mips_new_gp to
32 when -march=r3900 is passed.
* testsuite/gcc.target/mips/r3900-mult.c: New test.
Index: config/mips/mips.md
===================================================================
--- config/mips/mips.md (revision 140921)
+++ config/mips/mips.md (revision 140922)
@@ -1367,35 +1367,21 @@ (define_expand "mul<mode>3"
DONE;
})
-(define_insn "mulsi3_mul3"
- [(set (match_operand:SI 0 "register_operand" "=d,l")
- (mult:SI (match_operand:SI 1 "register_operand" "d,d")
- (match_operand:SI 2 "register_operand" "d,d")))
- (clobber (match_scratch:SI 3 "=l,X"))]
- "ISA_HAS_MUL3"
+(define_insn "mul<mode>3_mul3"
+ [(set (match_operand:GPR 0 "register_operand" "=d,l")
+ (mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
+ (match_operand:GPR 2 "register_operand" "d,d")))
+ (clobber (match_scratch:GPR 3 "=l,X"))]
+ "ISA_HAS_<D>MUL3"
{
if (which_alternative == 1)
- return "mult\t%1,%2";
- if (TARGET_MIPS3900)
+ return "<d>mult\t%1,%2";
+ if (<MODE>mode == SImode && TARGET_MIPS3900)
return "mult\t%0,%1,%2";
- return "mul\t%0,%1,%2";
+ return "<d>mul\t%0,%1,%2";
}
[(set_attr "type" "imul3,imul")
- (set_attr "mode" "SI")])
-
-(define_insn "muldi3_mul3"
- [(set (match_operand:DI 0 "register_operand" "=d,l")
- (mult:DI (match_operand:DI 1 "register_operand" "d,d")
- (match_operand:DI 2 "register_operand" "d,d")))
- (clobber (match_scratch:DI 3 "=l,X"))]
- "ISA_HAS_DMUL3"
-{
- if (which_alternative == 1)
- return "dmult\t%1,%2";
- return "dmul\t%0,%1,%2";
-}
- [(set_attr "type" "imul3,imul")
- (set_attr "mode" "DI")])
+ (set_attr "mode" "<MODE>")])
;; If a register gets allocated to LO, and we spill to memory, the reload
;; will include a move from LO to a GPR. Merge it into the multiplication
Index: testsuite/gcc.target/mips/mips.exp
===================================================================
--- testsuite/gcc.target/mips/mips.exp (revision 140921)
+++ testsuite/gcc.target/mips/mips.exp (revision 140922)
@@ -261,6 +261,7 @@ proc dg-mips-options {args} {
-mips[12] -
-mips32* -
-march=mips32* -
+ -march=r3900 -
-march=24k* -
-mabi=32 -
-mgp32 {
Index: testsuite/gcc.target/mips/r3900-mult.c
===================================================================
--- testsuite/gcc.target/mips/r3900-mult.c (revision 0)
+++ testsuite/gcc.target/mips/r3900-mult.c (revision 140922)
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-march=r3900" } */
+/* { dg-final { scan-assembler "\tmult\t\[^\n\]*,\[^\n\]*," } } */
+
+NOMIPS16 int
+f (int a, int b)
+{
+ return a * b;
+}