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Re: RESUBMIT: PowerPC -- support single-precision FPU
Michael Eager wrote:
Janis Johnson wrote:
Michael Eager wrote:
There were problems with the TARGET_SINGLE_FLOAT_MODE and
TARGET_DOUBLE_FLOAT_MODE macros in the previous patch, and it
turns out that they really didn't make much difference.
They have been removed from this patch.
Please take a closer look at this hunk. The earlier version of
the patch caused a warning, and in this one the indentation still
doesn't match the nesting. I think the last '&&' should be '||',
it doesn't make much sense.
@@ -6239,9 +6294,10 @@ function_arg (CUMULATIVE_ARGS *cum, enum
else if (abi == ABI_V4)
{
if (TARGET_HARD_FLOAT && TARGET_FPRS
- && (mode == SFmode || mode == DFmode
- || (mode == TFmode && !TARGET_IEEEQUAD)
- || mode == SDmode || mode == DDmode || mode == TDmode))
+ && (((TARGET_SINGLE_FLOAT && mode == SFmode)
+ || (TARGET_DOUBLE_FLOAT && (mode == SFmode || mode ==
DFmode)))
+ && ((mode == TFmode && !TARGET_IEEEQUAD)
+ || mode == SDmode || mode == DDmode || mode == TDmode)))
{
/* _Decimal128 must use an even/odd register pair. This
assumes
that the register number is odd when fregno is odd. */
Did you mean to change processing for modes TF, SD, DD, TD? If not,
is this what you want? (It also changes back the ordering of the
last two lines.)
if (TARGET_HARD_FLOAT && TARGET_FPRS
&& (((TARGET_SINGLE_FLOAT && mode == SFmode)
|| (TARGET_DOUBLE_FLOAT && (mode == SFmode || mode ==
DFmode)))
|| (mode == TFmode && !TARGET_IEEEQUAD)
|| mode == SDmode || mode == DDmode || mode == TDmode))
Yes, you are right.
The block is executed if HARD_FLOAT && FPRS with decimal float,
TF if not IEEE, or if the appropriate FP mode is supported.
Attached patch fixes this and another similar problem handling
decimal float mode.
--
Michael Eager eager@eagercon.com
1960 Park Blvd., Palo Alto, CA 94306 650-325-8077
diff -urNp --exclude '*.swp' --exclude DEV-PHASE --exclude .svn gcc-orig/gcc/config/rs6000/rs6000.c gcc/gcc/config/rs6000/rs6000.c
--- gcc-orig/gcc/config/rs6000/rs6000.c 2008-09-29 08:18:27.000000000 -0700
+++ gcc/gcc/config/rs6000/rs6000.c 2008-09-29 08:32:55.000000000 -0700
@@ -5729,10 +5729,10 @@ function_arg_advance (CUMULATIVE_ARGS *c
else if (DEFAULT_ABI == ABI_V4)
{
if (TARGET_HARD_FLOAT && TARGET_FPRS
- && ((TARGET_SINGLE_FLOAT && mode == SFmode)
- || (TARGET_DOUBLE_FLOAT
- && (mode == DFmode || mode == DDmode || mode == TDmode))
- || (mode == TFmode && !TARGET_IEEEQUAD)))
+ && ((TARGET_SINGLE_FLOAT && mode == SFmode)
+ || (TARGET_DOUBLE_FLOAT && mode == DFmode))
+ || mode == SDmode || mode == DDmode || mode == TDmode
+ || (mode == TFmode && !TARGET_IEEEQUAD))
{
/* _Decimal128 must use an even/odd register pair. This assumes
that the register number is odd when fregno is odd. */
@@ -6294,10 +6294,10 @@ function_arg (CUMULATIVE_ARGS *cum, enum
else if (abi == ABI_V4)
{
if (TARGET_HARD_FLOAT && TARGET_FPRS
- && (((TARGET_SINGLE_FLOAT && mode == SFmode)
- || (TARGET_DOUBLE_FLOAT && (mode == SFmode || mode == DFmode)))
- && ((mode == TFmode && !TARGET_IEEEQUAD)
- || mode == SDmode || mode == DDmode || mode == TDmode)))
+ && ((TARGET_SINGLE_FLOAT && mode == SFmode)
+ || (TARGET_DOUBLE_FLOAT && mode == DFmode))
+ || mode == SDmode || mode == DDmode || mode == TDmode
+ || (mode == TFmode && !TARGET_IEEEQUAD))
{
/* _Decimal128 must use an even/odd register pair. This assumes
that the register number is odd when fregno is odd. */