[PATCH, MIPS] Merge mul*3_mul3 patterns

[Adam Nemet <anemet at caviumnetworks dot com>]

This is a follow-up patch to the mail:

  http://gcc.gnu.org/ml/gcc-patches/2008-08/msg02080.html

to merge the thee operand SI and DI multiplication patterns into a template.

Bootstrapped and tested on mips64octeon-unknown-linux-gnu.  I tested the new
testcase with {-mabi=32\ -mips16,-mabi=32,-mabi=64,-mel}.

OK to install?

Adam

	* config/mips/mips.md (mulsi3_mul3, muldi3_mul3): Merge these ...
	(mul<mode>3_mul3): ... into this new template.

testsuite/
	* testsuite/gcc.target/mips/r3900-mult.c: New test.

Index: config/mips/mips.md
===================================================================
--- config/mips/mips.md	(revision 140670)
+++ config/mips/mips.md	(working copy)
@@ -1366,35 +1366,21 @@ (define_expand "mul<mode>3"
   DONE;
 })
 
-(define_insn "mulsi3_mul3"
-  [(set (match_operand:SI 0 "register_operand" "=d,l")
-	(mult:SI (match_operand:SI 1 "register_operand" "d,d")
-		 (match_operand:SI 2 "register_operand" "d,d")))
-   (clobber (match_scratch:SI 3 "=l,X"))]
-  "ISA_HAS_MUL3"
+(define_insn "mul<mode>3_mul3"
+  [(set (match_operand:GPR 0 "register_operand" "=d,l")
+	(mult:GPR (match_operand:GPR 1 "register_operand" "d,d")
+		  (match_operand:GPR 2 "register_operand" "d,d")))
+   (clobber (match_scratch:GPR 3 "=l,X"))]
+  "ISA_HAS_<D>MUL3"
 {
   if (which_alternative == 1)
-    return "mult\t%1,%2";
-  if (TARGET_MIPS3900)
+    return "<d>mult\t%1,%2";
+  if (<MODE>mode == SImode && TARGET_MIPS3900)
     return "mult\t%0,%1,%2";
-  return "mul\t%0,%1,%2";
+  return "<d>mul\t%0,%1,%2";
 }
   [(set_attr "type" "imul3,imul")
-   (set_attr "mode" "SI")])
-
-(define_insn "muldi3_mul3"
-  [(set (match_operand:DI 0 "register_operand" "=d,l")
-	(mult:DI (match_operand:DI 1 "register_operand" "d,d")
-		 (match_operand:DI 2 "register_operand" "d,d")))
-   (clobber (match_scratch:DI 3 "=l,X"))]
-  "ISA_HAS_DMUL3"
-{
-  if (which_alternative == 1)
-    return "dmult\t%1,%2";
-  return "dmul\t%0,%1,%2";
-}
-  [(set_attr "type" "imul3,imul")
-   (set_attr "mode" "DI")])
+   (set_attr "mode" "<MODE>")])
 
 ;; If a register gets allocated to LO, and we spill to memory, the reload
 ;; will include a move from LO to a GPR.  Merge it into the multiplication
Index: testsuite/gcc.target/mips/r3900-mult.c
===================================================================
--- testsuite/gcc.target/mips/r3900-mult.c	(revision 0)
+++ testsuite/gcc.target/mips/r3900-mult.c	(revision 0)
@@ -0,0 +1,9 @@
+/* { dg-do compile } */
+/* { dg-mips-options "-march=r3900 -mgp32" } */
+/* { dg-final { scan-assembler "\tmult\t\[^\n\]*,\[^\n\]*," } } */
+
+NOMIPS16 int
+f (int a, int b)
+{
+  return a * b;
+}