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Rest of optimize_size uses in i386 backend


Hi,
this patch replaces remaining uses of optimize_size in i386 backed by proper predicates.
Not everything can be decided per-BB basis, in particular things driven by insn recognizing
as instructions can be moved from hot to cold BB without being re-validated and we expect
this to work.  I've added new optimize_function_for_size for function wide decisions and
tried to minimize them.  Some of remaining uses still can be eliminated by reorganizing
i386 backend, but I doubt it will make big difference.

Bootstrapped/regtested x86_64-linux, will commit it shortly after i686 testing.

Honza

	* expmed.c (store_bit_field_1): Be prepared for movstrict expander to fail.
	* predict.c (always_optimize_for_size_p): Rename to ...
	(optimize_function_for_size): ... this one; make extern.
	(optimize_function_for_speed_p): New.
	(optimize_bb_for_size_p, optimize_bb_for_size_p,
	optimize_edge_for_size_p,optimize_edge_for_size_p,
	optimize_insn_for_size_p, optimize_insn_for_size_p): Update.
	* basic-block.h (optimize_function_for_size_p,
	optimize_function_for_speed_p): Declare.
	* i386.md (optimize_size checks): Replace them by appropriate predicate.
	(standard_80387_constant_p, ix86_compute_frame_layout,
	ix86_expand_epilogue, ix86_decompose_address,
	print_operand, emit_i387_cw_initialization,
	inline_memory_move_cost, ix86_pad_returns,
	ix86_reorg): Replace optimize_size checks.
Index: expmed.c
===================================================================
*** expmed.c	(revision 139728)
--- expmed.c	(working copy)
*************** store_bit_field_1 (rtx str_rtx, unsigned
*** 521,526 ****
--- 521,528 ----
  	  != CODE_FOR_nothing))
      {
        int icode = optab_handler (movstrict_optab, fieldmode)->insn_code;
+       rtx insn;
+       rtx start = get_last_insn ();
  
        /* Get appropriate low part of the value being stored.  */
        if (GET_CODE (value) == CONST_INT || REG_P (value))
*************** store_bit_field_1 (rtx str_rtx, unsigned
*** 544,556 ****
  	  op0 = SUBREG_REG (op0);
  	}
  
!       emit_insn (GEN_FCN (icode)
  		 (gen_rtx_SUBREG (fieldmode, op0,
  				  (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
  				  + (offset * UNITS_PER_WORD)),
  				  value));
! 
!       return true;
      }
  
    /* Handle fields bigger than a word.  */
--- 546,562 ----
  	  op0 = SUBREG_REG (op0);
  	}
  
!       insn = (GEN_FCN (icode)
  		 (gen_rtx_SUBREG (fieldmode, op0,
  				  (bitnum % BITS_PER_WORD) / BITS_PER_UNIT
  				  + (offset * UNITS_PER_WORD)),
  				  value));
!       if (insn)
! 	{
! 	  emit_insn (insn);
! 	  return true;
! 	}
!       delete_insns_since (start);
      }
  
    /* Handle fields bigger than a word.  */
Index: predict.c
===================================================================
*** predict.c	(revision 139531)
--- predict.c	(working copy)
*************** probably_never_executed_bb_p (const_basi
*** 182,192 ****
  
  /* Return true when current function should always be optimized for size.  */
  
! static bool
! always_optimize_for_size_p (void)
  {
    return (optimize_size
! 	  || cfun->function_frequency == FUNCTION_FREQUENCY_UNLIKELY_EXECUTED);
  }
  
  /* Return TRUE when BB should be optimized for size.  */
--- 182,200 ----
  
  /* Return true when current function should always be optimized for size.  */
  
! bool
! optimize_function_for_size_p (struct function *fun)
  {
    return (optimize_size
! 	  || fun->function_frequency == FUNCTION_FREQUENCY_UNLIKELY_EXECUTED);
! }
! 
! /* Return true when current function should always be optimized for speed.  */
! 
! bool
! optimize_function_for_speed_p (struct function *fun)
! {
!   return !optimize_function_for_size_p (fun);
  }
  
  /* Return TRUE when BB should be optimized for size.  */
*************** always_optimize_for_size_p (void)
*** 194,200 ****
  bool
  optimize_bb_for_size_p (basic_block bb)
  {
!   return always_optimize_for_size_p () || !maybe_hot_bb_p (bb);
  }
  
  /* Return TRUE when BB should be optimized for speed.  */
--- 202,208 ----
  bool
  optimize_bb_for_size_p (basic_block bb)
  {
!   return optimize_function_for_size_p (cfun) || !maybe_hot_bb_p (bb);
  }
  
  /* Return TRUE when BB should be optimized for speed.  */
*************** optimize_bb_for_speed_p (basic_block bb)
*** 210,216 ****
  bool
  optimize_edge_for_size_p (edge e)
  {
!   return always_optimize_for_size_p () || !maybe_hot_edge_p (e);
  }
  
  /* Return TRUE when BB should be optimized for speed.  */
--- 218,224 ----
  bool
  optimize_edge_for_size_p (edge e)
  {
!   return optimize_function_for_size_p (cfun) || !maybe_hot_edge_p (e);
  }
  
  /* Return TRUE when BB should be optimized for speed.  */
*************** optimize_edge_for_speed_p (edge e)
*** 226,232 ****
  bool
  optimize_insn_for_size_p (void)
  {
!   return always_optimize_for_size_p () || !crtl->maybe_hot_insn_p;
  }
  
  /* Return TRUE when BB should be optimized for speed.  */
--- 234,240 ----
  bool
  optimize_insn_for_size_p (void)
  {
!   return optimize_function_for_size_p (cfun) || !crtl->maybe_hot_insn_p;
  }
  
  /* Return TRUE when BB should be optimized for speed.  */
Index: basic-block.h
===================================================================
*** basic-block.h	(revision 139531)
--- basic-block.h	(working copy)
*************** extern bool optimize_edge_for_size_p (ed
*** 837,842 ****
--- 837,844 ----
  extern bool optimize_edge_for_speed_p (edge);
  extern bool optimize_insn_for_size_p (void);
  extern bool optimize_insn_for_speed_p (void);
+ extern bool optimize_function_for_size_p (struct function *);
+ extern bool optimize_function_for_speed_p (struct function *);
  extern bool gimple_predicted_by_p (const_basic_block, enum br_predictor);
  extern bool rtl_predicted_by_p (const_basic_block, enum br_predictor);
  extern void gimple_predict_edge (edge, enum br_predictor, int);
Index: config/i386/i386.md
===================================================================
*** config/i386/i386.md	(revision 139728)
--- config/i386/i386.md	(working copy)
***************
*** 1236,1242 ****
  	       [(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
  	  UNSPEC_FNSTSW))]
    "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
!    && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
     && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
    "* return output_fp_compare (insn, operands, 0, 0);"
    [(set_attr "type" "multi")
--- 1236,1242 ----
  	       [(match_operand:X87MODEI12 2 "memory_operand" "m")]))]
  	  UNSPEC_FNSTSW))]
    "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
!    && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
     && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
    "* return output_fp_compare (insn, operands, 0, 0);"
    [(set_attr "type" "multi")
***************
*** 1253,1259 ****
     (clobber (match_operand:HI 0 "register_operand" "=a"))]
    "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
     && TARGET_SAHF && !TARGET_CMOVE
!    && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
     && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
    "#"
    "&& reload_completed"
--- 1253,1259 ----
     (clobber (match_operand:HI 0 "register_operand" "=a"))]
    "X87_FLOAT_MODE_P (GET_MODE (operands[1]))
     && TARGET_SAHF && !TARGET_CMOVE
!    && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
     && (GET_MODE (operands [3]) == GET_MODE (operands[1]))"
    "#"
    "&& reload_completed"
***************
*** 1665,1671 ****
      }
  }
    [(set (attr "type")
!      (cond [(ne (symbol_ref "optimize_size") (const_int 0))
  	      (const_string "imov")
  	    (and (eq_attr "alternative" "0")
  		 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
--- 1665,1671 ----
      }
  }
    [(set (attr "type")
!      (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
  	      (const_string "imov")
  	    (and (eq_attr "alternative" "0")
  		 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
***************
*** 1733,1739 ****
  	(match_operand:HI 1 "register_operand" "+r"))
     (set (match_dup 1)
  	(match_dup 0))]
!   "!TARGET_PARTIAL_REG_STALL || optimize_size"
    "xchg{l}\t%k1, %k0"
    [(set_attr "type" "imov")
     (set_attr "mode" "SI")
--- 1733,1739 ----
  	(match_operand:HI 1 "register_operand" "+r"))
     (set (match_dup 1)
  	(match_dup 0))]
!   "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
    "xchg{l}\t%k1, %k0"
    [(set_attr "type" "imov")
     (set_attr "mode" "SI")
***************
*** 1757,1764 ****
  (define_expand "movstricthi"
    [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
  	(match_operand:HI 1 "general_operand" ""))]
!   "! TARGET_PARTIAL_REG_STALL || optimize_size"
  {
    /* Don't generate memory->memory moves, go through a register */
    if (MEM_P (operands[0]) && MEM_P (operands[1]))
      operands[1] = force_reg (HImode, operands[1]);
--- 1757,1766 ----
  (define_expand "movstricthi"
    [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" ""))
  	(match_operand:HI 1 "general_operand" ""))]
!   ""
  {
+   if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
+     FAIL;
    /* Don't generate memory->memory moves, go through a register */
    if (MEM_P (operands[0]) && MEM_P (operands[1]))
      operands[1] = force_reg (HImode, operands[1]);
***************
*** 1767,1773 ****
  (define_insn "*movstricthi_1"
    [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
  	(match_operand:HI 1 "general_operand" "rn,m"))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "mov{w}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imov")
--- 1769,1775 ----
  (define_insn "*movstricthi_1"
    [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+rm,r"))
  	(match_operand:HI 1 "general_operand" "rn,m"))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "mov{w}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imov")
***************
*** 1841,1847 ****
       (cond [(and (eq_attr "alternative" "5")
  		 (not (match_operand:QI 1 "aligned_operand" "")))
  	      (const_string "imovx")
! 	    (ne (symbol_ref "optimize_size") (const_int 0))
  	      (const_string "imov")
  	    (and (eq_attr "alternative" "3")
  		 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
--- 1843,1849 ----
       (cond [(and (eq_attr "alternative" "5")
  		 (not (match_operand:QI 1 "aligned_operand" "")))
  	      (const_string "imovx")
! 	    (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
  	      (const_string "imov")
  	    (and (eq_attr "alternative" "3")
  		 (ior (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
***************
*** 1868,1874 ****
  		  (and (eq_attr "alternative" "0,1")
  		       (and (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
  				(const_int 0))
! 			    (and (eq (symbol_ref "optimize_size")
  				     (const_int 0))
  			    	 (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
  				     (const_int 0))))))
--- 1870,1876 ----
  		  (and (eq_attr "alternative" "0,1")
  		       (and (ne (symbol_ref "TARGET_PARTIAL_REG_DEPENDENCY")
  				(const_int 0))
! 			    (and (eq (symbol_ref "optimize_function_for_size_p (cfun)")
  				     (const_int 0))
  			    	 (eq (symbol_ref "TARGET_PARTIAL_REG_STALL")
  				     (const_int 0))))))
***************
*** 1889,1895 ****
  	(match_operand:QI 1 "register_operand" "+r"))
     (set (match_dup 1)
  	(match_dup 0))]
!   "!TARGET_PARTIAL_REG_STALL || optimize_size"
    "xchg{l}\t%k1, %k0"
    [(set_attr "type" "imov")
     (set_attr "mode" "SI")
--- 1891,1897 ----
  	(match_operand:QI 1 "register_operand" "+r"))
     (set (match_dup 1)
  	(match_dup 0))]
!   "!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
    "xchg{l}\t%k1, %k0"
    [(set_attr "type" "imov")
     (set_attr "mode" "SI")
***************
*** 1913,1920 ****
  (define_expand "movstrictqi"
    [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
  	(match_operand:QI 1 "general_operand" ""))]
!   "! TARGET_PARTIAL_REG_STALL || optimize_size"
  {
    /* Don't generate memory->memory moves, go through a register.  */
    if (MEM_P (operands[0]) && MEM_P (operands[1]))
      operands[1] = force_reg (QImode, operands[1]);
--- 1915,1924 ----
  (define_expand "movstrictqi"
    [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
  	(match_operand:QI 1 "general_operand" ""))]
!   ""
  {
+   if (TARGET_PARTIAL_REG_STALL && optimize_function_for_speed_p (cfun))
+     FAIL;
    /* Don't generate memory->memory moves, go through a register.  */
    if (MEM_P (operands[0]) && MEM_P (operands[1]))
      operands[1] = force_reg (QImode, operands[1]);
***************
*** 1923,1929 ****
  (define_insn "*movstrictqi_1"
    [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
  	(match_operand:QI 1 "general_operand" "*qn,m"))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "mov{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imov")
--- 1927,1933 ----
  (define_insn "*movstrictqi_1"
    [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+qm,q"))
  	(match_operand:QI 1 "general_operand" "*qn,m"))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "mov{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imov")
***************
*** 2573,2579 ****
     (set_attr "prefix" "maybe_vex")
     (set (attr "mode")
  	(cond [(ior (eq (symbol_ref "TARGET_SSE2") (const_int 0))
! 		    (ne (symbol_ref "optimize_size") (const_int 0)))
  		 (const_string "V4SF")
  	       (and (eq_attr "alternative" "2")
  		    (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
--- 2577,2583 ----
     (set_attr "prefix" "maybe_vex")
     (set (attr "mode")
  	(cond [(ior (eq (symbol_ref "TARGET_SSE2") (const_int 0))
! 		    (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0)))
  		 (const_string "V4SF")
  	       (and (eq_attr "alternative" "2")
  		    (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
***************
*** 2625,2631 ****
     (set (attr "mode")
          (cond [(eq_attr "alternative" "2,3")
  		 (if_then_else
! 		   (ne (symbol_ref "optimize_size")
  		       (const_int 0))
  		   (const_string "V4SF")
  		   (const_string "TI"))
--- 2629,2635 ----
     (set (attr "mode")
          (cond [(eq_attr "alternative" "2,3")
  		 (if_then_else
! 		   (ne (symbol_ref "optimize_function_for_size_p (cfun)")
  		       (const_int 0))
  		   (const_string "V4SF")
  		   (const_string "TI"))
***************
*** 2633,2639 ****
  		 (if_then_else
  		   (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
  			    (const_int 0))
! 			(ne (symbol_ref "optimize_size")
  			    (const_int 0)))
  		   (const_string "V4SF")
  		   (const_string "TI"))]
--- 2637,2643 ----
  		 (if_then_else
  		   (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
  			    (const_int 0))
! 			(ne (symbol_ref "optimize_function_for_size_p (cfun)")
  			    (const_int 0)))
  		   (const_string "V4SF")
  		   (const_string "TI"))]
***************
*** 2728,2734 ****
    "!(MEM_P (operands[0]) && MEM_P (operands[1]))
     && (reload_in_progress || reload_completed
         || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
!        || (!TARGET_SSE_MATH && optimize_size
  	   && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], SFmode))"
--- 2732,2738 ----
    "!(MEM_P (operands[0]) && MEM_P (operands[1]))
     && (reload_in_progress || reload_completed
         || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
!        || (!TARGET_SSE_MATH && optimize_function_for_size_p (cfun)
  	   && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], SFmode))"
***************
*** 2790,2796 ****
  			    	 (const_int 0))
  			     (ne (symbol_ref "TARGET_SSE2")
  				 (const_int 0)))
! 			(eq (symbol_ref "optimize_size")
  			    (const_int 0)))
  		   (const_string "TI")
  		   (const_string "V4SF"))
--- 2794,2800 ----
  			    	 (const_int 0))
  			     (ne (symbol_ref "TARGET_SSE2")
  				 (const_int 0)))
! 			(eq (symbol_ref "optimize_function_for_size_p (cfun)")
  			    (const_int 0)))
  		   (const_string "TI")
  		   (const_string "V4SF"))
***************
*** 2892,2905 ****
  	(match_operand:DF 1 "general_operand"
  			"fm,f,G,*roF,*Fr,C   ,Y2*x,mY2*x,Y2*x"))]
    "!(MEM_P (operands[0]) && MEM_P (operands[1]))
!    && ((optimize_size || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
     && (reload_in_progress || reload_completed
         || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
!        || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
             && !memory_operand (operands[0], DFmode)
  	   && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
!        || ((optimize_size
              || !TARGET_MEMORY_MISMATCH_STALL
  	    || reload_in_progress || reload_completed)
   	   && memory_operand (operands[0], DFmode)))"
--- 2896,2911 ----
  	(match_operand:DF 1 "general_operand"
  			"fm,f,G,*roF,*Fr,C   ,Y2*x,mY2*x,Y2*x"))]
    "!(MEM_P (operands[0]) && MEM_P (operands[1]))
!    && ((optimize_function_for_size_p (cfun)
!        || !TARGET_INTEGER_DFMODE_MOVES) && !TARGET_64BIT)
     && (reload_in_progress || reload_completed
         || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
!        || (!(TARGET_SSE2 && TARGET_SSE_MATH)
!            && optimize_function_for_size_p (cfun)
             && !memory_operand (operands[0], DFmode)
  	   && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
!        || ((optimize_function_for_size_p (cfun)
              || !TARGET_MEMORY_MISMATCH_STALL
  	    || reload_in_progress || reload_completed)
   	   && memory_operand (operands[0], DFmode)))"
***************
*** 2999,3005 ****
  
  	       /* xorps is one byte shorter.  */
  	       (eq_attr "alternative" "5")
! 		 (cond [(ne (symbol_ref "optimize_size")
  			    (const_int 0))
  			  (const_string "V4SF")
  			(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
--- 3005,3011 ----
  
  	       /* xorps is one byte shorter.  */
  	       (eq_attr "alternative" "5")
! 		 (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
  			    (const_int 0))
  			  (const_string "V4SF")
  			(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
***************
*** 3015,3021 ****
  		  movaps encodes one byte shorter.  */
  	       (eq_attr "alternative" "6")
  		 (cond
! 		   [(ne (symbol_ref "optimize_size")
  		        (const_int 0))
  		      (const_string "V4SF")
  		    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
--- 3021,3027 ----
  		  movaps encodes one byte shorter.  */
  	       (eq_attr "alternative" "6")
  		 (cond
! 		   [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
  		        (const_int 0))
  		      (const_string "V4SF")
  		    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
***************
*** 3043,3049 ****
    "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
     && (reload_in_progress || reload_completed
         || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
!        || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
  	   && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], DFmode))"
--- 3049,3056 ----
    "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))
     && (reload_in_progress || reload_completed
         || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
!        || (!(TARGET_SSE2 && TARGET_SSE_MATH)
!            && optimize_function_for_size_p (cfun)
  	   && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], DFmode))"
***************
*** 3132,3138 ****
  
  	       /* xorps is one byte shorter.  */
  	       (eq_attr "alternative" "5")
! 		 (cond [(ne (symbol_ref "optimize_size")
  			    (const_int 0))
  			  (const_string "V4SF")
  			(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
--- 3139,3145 ----
  
  	       /* xorps is one byte shorter.  */
  	       (eq_attr "alternative" "5")
! 		 (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
  			    (const_int 0))
  			  (const_string "V4SF")
  			(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
***************
*** 3148,3154 ****
  		  movaps encodes one byte shorter.  */
  	       (eq_attr "alternative" "6")
  		 (cond
! 		   [(ne (symbol_ref "optimize_size")
  		        (const_int 0))
  		      (const_string "V4SF")
  		    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
--- 3155,3161 ----
  		  movaps encodes one byte shorter.  */
  	       (eq_attr "alternative" "6")
  		 (cond
! 		   [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
  		        (const_int 0))
  		      (const_string "V4SF")
  		    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
***************
*** 3174,3183 ****
  	(match_operand:DF 1 "general_operand"
  		"fm,f,G,roF,Fr,C   ,Y2*x,m   ,Y2*x"))]
    "!(MEM_P (operands[0]) && MEM_P (operands[1]))
!    && !optimize_size && TARGET_INTEGER_DFMODE_MOVES
     && (reload_in_progress || reload_completed
         || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
!        || (!(TARGET_SSE2 && TARGET_SSE_MATH) && optimize_size
  	   && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], DFmode))"
--- 3181,3192 ----
  	(match_operand:DF 1 "general_operand"
  		"fm,f,G,roF,Fr,C   ,Y2*x,m   ,Y2*x"))]
    "!(MEM_P (operands[0]) && MEM_P (operands[1]))
!    && optimize_function_for_speed_p (cfun)
!    && TARGET_INTEGER_DFMODE_MOVES
     && (reload_in_progress || reload_completed
         || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
!        || (!(TARGET_SSE2 && TARGET_SSE_MATH)
!            && optimize_function_for_size_p (cfun)
  	   && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], DFmode))"
***************
*** 3250,3256 ****
  
  	       /* xorps is one byte shorter.  */
  	       (eq_attr "alternative" "5")
! 		 (cond [(ne (symbol_ref "optimize_size")
  			    (const_int 0))
  			  (const_string "V4SF")
  			(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
--- 3259,3265 ----
  
  	       /* xorps is one byte shorter.  */
  	       (eq_attr "alternative" "5")
! 		 (cond [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
  			    (const_int 0))
  			  (const_string "V4SF")
  			(ne (symbol_ref "TARGET_SSE_LOAD0_BY_PXOR")
***************
*** 3266,3272 ****
  		  movaps encodes one byte shorter.  */
  	       (eq_attr "alternative" "6")
  		 (cond
! 		   [(ne (symbol_ref "optimize_size")
  		        (const_int 0))
  		      (const_string "V4SF")
  		    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
--- 3275,3281 ----
  		  movaps encodes one byte shorter.  */
  	       (eq_attr "alternative" "6")
  		 (cond
! 		   [(ne (symbol_ref "optimize_function_for_size_p (cfun)")
  		        (const_int 0))
  		      (const_string "V4SF")
  		    (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
***************
*** 3331,3337 ****
  (define_insn "*pushxf_nointeger"
    [(set (match_operand:XF 0 "push_operand" "=X,X,X")
  	(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
!   "optimize_size"
  {
    /* This insn should be already split before reg-stack.  */
    gcc_unreachable ();
--- 3340,3346 ----
  (define_insn "*pushxf_nointeger"
    [(set (match_operand:XF 0 "push_operand" "=X,X,X")
  	(match_operand:XF 1 "general_no_elim_operand" "f,Fo,*r"))]
!   "optimize_function_for_size_p (cfun)"
  {
    /* This insn should be already split before reg-stack.  */
    gcc_unreachable ();
***************
*** 3343,3349 ****
  (define_insn "*pushxf_integer"
    [(set (match_operand:XF 0 "push_operand" "=<,<")
  	(match_operand:XF 1 "general_no_elim_operand" "f,ro"))]
!   "!optimize_size"
  {
    /* This insn should be already split before reg-stack.  */
    gcc_unreachable ();
--- 3352,3358 ----
  (define_insn "*pushxf_integer"
    [(set (match_operand:XF 0 "push_operand" "=<,<")
  	(match_operand:XF 1 "general_no_elim_operand" "f,ro"))]
!   "optimize_function_for_speed_p (cfun)"
  {
    /* This insn should be already split before reg-stack.  */
    gcc_unreachable ();
***************
*** 3374,3383 ****
  (define_insn "*movxf_nointeger"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
  	(match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
!   "optimize_size
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))
     && (reload_in_progress || reload_completed
!        || (optimize_size && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], XFmode))"
  {
--- 3383,3392 ----
  (define_insn "*movxf_nointeger"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,*r,o")
  	(match_operand:XF 1 "general_operand" "fm,f,G,*roF,F*r"))]
!   "optimize_function_for_size_p (cfun)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))
     && (reload_in_progress || reload_completed
!        || standard_80387_constant_p (operands[1])
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], XFmode))"
  {
***************
*** 3402,3411 ****
  (define_insn "*movxf_integer"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,r,o")
  	(match_operand:XF 1 "general_operand" "fm,f,G,roF,Fr"))]
!   "!optimize_size
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))
     && (reload_in_progress || reload_completed
-        || (optimize_size && standard_80387_constant_p (operands[1]))
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], XFmode))"
  {
--- 3411,3419 ----
  (define_insn "*movxf_integer"
    [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,r,o")
  	(match_operand:XF 1 "general_operand" "fm,f,G,roF,Fr"))]
!   "optimize_function_for_speed_p (cfun)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))
     && (reload_in_progress || reload_completed
         || GET_CODE (operands[1]) != CONST_DOUBLE
         || memory_operand (operands[0], XFmode))"
  {
***************
*** 3468,3474 ****
     (set (attr "mode")
          (cond [(eq_attr "alternative" "0,2")
  		 (if_then_else
! 		   (ne (symbol_ref "optimize_size")
  		       (const_int 0))
  		   (const_string "V4SF")
  		   (const_string "TI"))
--- 3476,3482 ----
     (set (attr "mode")
          (cond [(eq_attr "alternative" "0,2")
  		 (if_then_else
! 		   (ne (symbol_ref "optimize_function_for_size_p (cfun)")
  		       (const_int 0))
  		   (const_string "V4SF")
  		   (const_string "TI"))
***************
*** 3476,3482 ****
  		 (if_then_else
  		   (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
  			    (const_int 0))
! 			(ne (symbol_ref "optimize_size")
  			    (const_int 0)))
  		   (const_string "V4SF")
  		   (const_string "TI"))]
--- 3484,3490 ----
  		 (if_then_else
  		   (ior (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
  			    (const_int 0))
! 			(ne (symbol_ref "optimize_function_for_size_p (cfun)")
  			    (const_int 0)))
  		   (const_string "V4SF")
  		   (const_string "TI"))]
***************
*** 3639,3645 ****
       (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
    ""
  {
!   if (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
      {
        operands[1] = force_reg (HImode, operands[1]);
        emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
--- 3647,3653 ----
       (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
    ""
  {
!   if (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
      {
        operands[1] = force_reg (HImode, operands[1]);
        emit_insn (gen_zero_extendhisi2_and (operands[0], operands[1]));
***************
*** 3651,3657 ****
    [(set (match_operand:SI 0 "register_operand" "=r")
       (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
    "#"
    [(set_attr "type" "alu1")
     (set_attr "mode" "SI")])
--- 3659,3665 ----
    [(set (match_operand:SI 0 "register_operand" "=r")
       (zero_extend:SI (match_operand:HI 1 "register_operand" "0")))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
    "#"
    [(set_attr "type" "alu1")
     (set_attr "mode" "SI")])
***************
*** 3660,3666 ****
    [(set (match_operand:SI 0 "register_operand" "")
  	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "reload_completed && TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
    [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
  	      (clobber (reg:CC FLAGS_REG))])]
    "")
--- 3668,3675 ----
    [(set (match_operand:SI 0 "register_operand" "")
  	(zero_extend:SI (match_operand:HI 1 "register_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "reload_completed && TARGET_ZERO_EXTEND_WITH_AND
!    && optimize_function_for_speed_p (cfun)"
    [(parallel [(set (match_dup 0) (and:SI (match_dup 0) (const_int 65535)))
  	      (clobber (reg:CC FLAGS_REG))])]
    "")
***************
*** 3668,3674 ****
  (define_insn "*zero_extendhisi2_movzwl"
    [(set (match_operand:SI 0 "register_operand" "=r")
       (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
!   "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
    "movz{wl|x}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "SI")])
--- 3677,3684 ----
  (define_insn "*zero_extendhisi2_movzwl"
    [(set (match_operand:SI 0 "register_operand" "=r")
       (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
!   "!TARGET_ZERO_EXTEND_WITH_AND
!    || optimize_function_for_size_p (cfun)"
    "movz{wl|x}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "SI")])
***************
*** 3685,3691 ****
    [(set (match_operand:HI 0 "register_operand" "=r,?&q")
       (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
    "#"
    [(set_attr "type" "alu1")
     (set_attr "mode" "HI")])
--- 3695,3701 ----
    [(set (match_operand:HI 0 "register_operand" "=r,?&q")
       (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
    "#"
    [(set_attr "type" "alu1")
     (set_attr "mode" "HI")])
***************
*** 3694,3700 ****
    [(set (match_operand:HI 0 "register_operand" "=r,r")
       (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
     (clobber (reg:CC FLAGS_REG))]
!   "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
    "#"
    [(set_attr "type" "imovx,alu1")
     (set_attr "mode" "HI")])
--- 3704,3710 ----
    [(set (match_operand:HI 0 "register_operand" "=r,r")
       (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
     (clobber (reg:CC FLAGS_REG))]
!   "!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)"
    "#"
    [(set_attr "type" "imovx,alu1")
     (set_attr "mode" "HI")])
***************
*** 3703,3709 ****
  (define_insn "*zero_extendqihi2_movzbl"
    [(set (match_operand:HI 0 "register_operand" "=r")
       (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
!   "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
    "movz{bl|x}\t{%1, %k0|%k0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "SI")])
--- 3713,3720 ----
  (define_insn "*zero_extendqihi2_movzbl"
    [(set (match_operand:HI 0 "register_operand" "=r")
       (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
!   "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_speed_p (cfun))
!    && reload_completed"
    "movz{bl|x}\t{%1, %k0|%k0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "SI")])
***************
*** 3714,3720 ****
  	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed
!    && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
     && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
    [(set (match_operand:HI 0 "register_operand" "")
  	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
--- 3725,3732 ----
  	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed
!    && (!TARGET_ZERO_EXTEND_WITH_AND
!        || optimize_function_for_size_p (cfun))
     && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
    [(set (match_operand:HI 0 "register_operand" "")
  	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))])
***************
*** 3727,3733 ****
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed
     && ANY_QI_REG_P (operands[0])
!    && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
     && !reg_overlap_mentioned_p (operands[0], operands[1])"
    [(set (match_dup 0) (const_int 0))
     (set (strict_low_part (match_dup 2)) (match_dup 1))]
--- 3739,3746 ----
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed
     && ANY_QI_REG_P (operands[0])
!    && (TARGET_ZERO_EXTEND_WITH_AND
!        && optimize_function_for_speed_p (cfun))
     && !reg_overlap_mentioned_p (operands[0], operands[1])"
    [(set (match_dup 0) (const_int 0))
     (set (strict_low_part (match_dup 2)) (match_dup 1))]
***************
*** 3756,3762 ****
    [(set (match_operand:SI 0 "register_operand" "=r,?&q")
       (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_ZERO_EXTEND_WITH_AND && !optimize_size"
    "#"
    [(set_attr "type" "alu1")
     (set_attr "mode" "SI")])
--- 3769,3775 ----
    [(set (match_operand:SI 0 "register_operand" "=r,?&q")
       (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0,qm")))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun)"
    "#"
    [(set_attr "type" "alu1")
     (set_attr "mode" "SI")])
***************
*** 3765,3771 ****
    [(set (match_operand:SI 0 "register_operand" "=r,r")
       (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
     (clobber (reg:CC FLAGS_REG))]
!   "!TARGET_ZERO_EXTEND_WITH_AND || optimize_size"
    "#"
    [(set_attr "type" "imovx,alu1")
     (set_attr "mode" "SI")])
--- 3778,3784 ----
    [(set (match_operand:SI 0 "register_operand" "=r,r")
       (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm,0")))
     (clobber (reg:CC FLAGS_REG))]
!   "!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun)"
    "#"
    [(set_attr "type" "imovx,alu1")
     (set_attr "mode" "SI")])
***************
*** 3773,3779 ****
  (define_insn "*zero_extendqisi2_movzbw"
    [(set (match_operand:SI 0 "register_operand" "=r")
       (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
!   "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_size) && reload_completed"
    "movz{bl|x}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "SI")])
--- 3786,3793 ----
  (define_insn "*zero_extendqisi2_movzbw"
    [(set (match_operand:SI 0 "register_operand" "=r")
       (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "qm")))]
!   "(!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
!    && reload_completed"
    "movz{bl|x}\t{%1, %0|%0, %1}"
    [(set_attr "type" "imovx")
     (set_attr "mode" "SI")])
***************
*** 3784,3790 ****
  	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed
!    && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
     && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
    [(set (match_dup 0)
  	(zero_extend:SI (match_dup 1)))])
--- 3798,3804 ----
  	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "reload_completed
!    && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_function_for_size_p (cfun))
     && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
    [(set (match_dup 0)
  	(zero_extend:SI (match_dup 1)))])
***************
*** 3798,3804 ****
    "reload_completed
     && ANY_QI_REG_P (operands[0])
     && (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
!    && (TARGET_ZERO_EXTEND_WITH_AND && !optimize_size)
     && !reg_overlap_mentioned_p (operands[0], operands[1])"
    [(set (match_dup 0) (const_int 0))
     (set (strict_low_part (match_dup 2)) (match_dup 1))]
--- 3812,3818 ----
    "reload_completed
     && ANY_QI_REG_P (operands[0])
     && (ANY_QI_REG_P (operands[1]) || MEM_P (operands[1]))
!    && (TARGET_ZERO_EXTEND_WITH_AND && optimize_function_for_speed_p (cfun))
     && !reg_overlap_mentioned_p (operands[0], operands[1])"
    [(set (match_dup 0) (const_int 0))
     (set (strict_low_part (match_dup 2)) (match_dup 1))]
***************
*** 3985,3991 ****
    emit_move_insn (operands[3], operands[1]);
  
    /* Generate a cltd if possible and doing so it profitable.  */
!   if ((optimize_size || TARGET_USE_CLTD)
        && true_regnum (operands[1]) == AX_REG
        && true_regnum (operands[2]) == DX_REG)
      {
--- 3999,4005 ----
    emit_move_insn (operands[3], operands[1]);
  
    /* Generate a cltd if possible and doing so it profitable.  */
!   if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
        && true_regnum (operands[1]) == AX_REG
        && true_regnum (operands[2]) == DX_REG)
      {
***************
*** 4016,4022 ****
      emit_move_insn (operands[3], operands[1]);
  
    /* Generate a cltd if possible and doing so it profitable.  */
!   if ((optimize_size || TARGET_USE_CLTD)
        && true_regnum (operands[3]) == AX_REG)
      {
        emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
--- 4030,4036 ----
      emit_move_insn (operands[3], operands[1]);
  
    /* Generate a cltd if possible and doing so it profitable.  */
!   if ((optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)
        && true_regnum (operands[3]) == AX_REG)
      {
        emit_insn (gen_ashrsi3_31 (operands[4], operands[3], GEN_INT (31)));
***************
*** 4199,4205 ****
    [(set (match_operand:DF 0 "register_operand" "")
          (float_extend:DF
  	  (match_operand:SF 1 "nonimmediate_operand" "")))]
!   "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
     && reload_completed && SSE_REG_P (operands[0])"
     [(set (match_dup 2)
  	 (float_extend:V2DF
--- 4213,4220 ----
    [(set (match_operand:DF 0 "register_operand" "")
          (float_extend:DF
  	  (match_operand:SF 1 "nonimmediate_operand" "")))]
!   "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC)
!    && optimize_insn_for_speed_p ()
     && reload_completed && SSE_REG_P (operands[0])"
     [(set (match_dup 2)
  	 (float_extend:V2DF
***************
*** 4338,4344 ****
    [(set (match_operand:SF 0 "register_operand" "")
          (float_truncate:SF
  	  (match_operand:DF 1 "nonimmediate_operand" "")))]
!   "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC) && !optimize_size
     && reload_completed && SSE_REG_P (operands[0])"
     [(set (match_dup 2)
  	 (vec_concat:V4SF
--- 4353,4360 ----
    [(set (match_operand:SF 0 "register_operand" "")
          (float_truncate:SF
  	  (match_operand:DF 1 "nonimmediate_operand" "")))]
!   "(TARGET_USE_VECTOR_CONVERTS || TARGET_GENERIC)
!    && optimize_insn_for_speed_p ()
     && reload_completed && SSE_REG_P (operands[0])"
     [(set (match_dup 2)
  	 (vec_concat:V4SF
***************
*** 4701,4707 ****
     (use (match_operand:<ssevecmode> 4  "nonimmediate_operand" "m,x"))
     (clobber (match_scratch:<ssevecmode> 1 "=x,&x"))
     (clobber (match_scratch:<ssevecmode> 2 "=x,x"))]
!   "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !optimize_size"
    "#"
    "&& reload_completed"
    [(const_int 0)]
--- 4717,4724 ----
     (use (match_operand:<ssevecmode> 4  "nonimmediate_operand" "m,x"))
     (clobber (match_scratch:<ssevecmode> 1 "=x,&x"))
     (clobber (match_scratch:<ssevecmode> 2 "=x,x"))]
!   "!TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH
!    && optimize_function_for_speed_p (cfun)"
    "#"
    "&& reload_completed"
    [(const_int 0)]
***************
*** 4763,4769 ****
    [(match_scratch:DF 2 "Y2")
     (set (match_operand:SSEMODEI24 0 "register_operand" "")
  	(fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
!   "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
    [(set (match_dup 2) (match_dup 1))
     (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
    "")
--- 4780,4786 ----
    [(match_scratch:DF 2 "Y2")
     (set (match_operand:SSEMODEI24 0 "register_operand" "")
  	(fix:SSEMODEI24 (match_operand:DF 1 "memory_operand" "")))]
!   "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
    [(set (match_dup 2) (match_dup 1))
     (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
    "")
***************
*** 4772,4778 ****
    [(match_scratch:SF 2 "x")
     (set (match_operand:SSEMODEI24 0 "register_operand" "")
  	(fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
!   "TARGET_AVOID_VECTOR_DECODE && !optimize_size"
    [(set (match_dup 2) (match_dup 1))
     (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
    "")
--- 4789,4795 ----
    [(match_scratch:SF 2 "x")
     (set (match_operand:SSEMODEI24 0 "register_operand" "")
  	(fix:SSEMODEI24 (match_operand:SF 1 "memory_operand" "")))]
!   "TARGET_AVOID_VECTOR_DECODE && optimize_insn_for_speed_p ()"
    [(set (match_dup 2) (match_dup 1))
     (set (match_dup 0) (fix:SSEMODEI24 (match_dup 2)))]
    "")
***************
*** 5115,5123 ****
      || ((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
  	&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH
  	&& ((<SSEMODEI24:MODE>mode == SImode
! 	     && TARGET_SSE2 && TARGET_USE_VECTOR_CONVERTS && !optimize_size
  	     && flag_trapping_math)
! 	    || !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size))))
     && !(reload_completed || reload_in_progress)"
    "#"
    "&& 1"
--- 5132,5142 ----
      || ((<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
  	&& SSE_FLOAT_MODE_P (<X87MODEF:MODE>mode) && TARGET_SSE_MATH
  	&& ((<SSEMODEI24:MODE>mode == SImode
! 	     && TARGET_SSE2 && TARGET_USE_VECTOR_CONVERTS
! 	     && optimize_function_for_speed_p (cfun)
  	     && flag_trapping_math)
! 	    || !(TARGET_INTER_UNIT_CONVERSIONS
! 	         || optimize_function_for_size_p (cfun)))))
     && !(reload_completed || reload_in_progress)"
    "#"
    "&& 1"
***************
*** 5130,5136 ****
       by passing DImode value through XMM registers.  */
    if (<SSEMODEI24:MODE>mode == DImode && !TARGET_64BIT 
        && TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES 
!       && !optimize_size)
      {
        emit_insn (gen_floatdi<X87MODEF:mode>2_i387_with_xmm (operands[0],
  							    operands[1],
--- 5149,5155 ----
       by passing DImode value through XMM registers.  */
    if (<SSEMODEI24:MODE>mode == DImode && !TARGET_64BIT 
        && TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES 
!       && optimize_function_for_speed_p (cfun))
      {
        emit_insn (gen_floatdi<X87MODEF:mode>2_i387_with_xmm (operands[0],
  							    operands[1],
***************
*** 5145,5151 ****
  	  (match_operand:SI 1 "nonimmediate_operand" "m,?r,r,m,!x")))
     (clobber (match_operand:SI 2 "memory_operand" "=X,m,m,X,m"))]
    "TARGET_SSE2 && TARGET_MIX_SSE_I387
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
    "#"
    [(set_attr "type" "fmov,multi,sseicvt,sseicvt,sseicvt")
     (set_attr "mode" "<MODE>,<MODE>,<MODE>,<MODE>,<ssevecmode>")
--- 5164,5170 ----
  	  (match_operand:SI 1 "nonimmediate_operand" "m,?r,r,m,!x")))
     (clobber (match_operand:SI 2 "memory_operand" "=X,m,m,X,m"))]
    "TARGET_SSE2 && TARGET_MIX_SSE_I387
!    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
    "#"
    [(set_attr "type" "fmov,multi,sseicvt,sseicvt,sseicvt")
     (set_attr "mode" "<MODE>,<MODE>,<MODE>,<MODE>,<ssevecmode>")
***************
*** 5158,5164 ****
    [(set (match_operand:MODEF 0 "register_operand" "=f,x")
  	(float:MODEF (match_operand:SI 1 "memory_operand" "m,m")))]
    "TARGET_SSE2 && TARGET_MIX_SSE_I387
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
    "@
     fild%z1\t%1
     #"
--- 5177,5183 ----
    [(set (match_operand:MODEF 0 "register_operand" "=f,x")
  	(float:MODEF (match_operand:SI 1 "memory_operand" "m,m")))]
    "TARGET_SSE2 && TARGET_MIX_SSE_I387
!    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
    "@
     fild%z1\t%1
     #"
***************
*** 5204,5210 ****
     (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
!    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size)
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
--- 5223,5229 ----
     (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
!    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
***************
*** 5219,5225 ****
  	  (match_operand:SSEMODEI24 1 "nonimmediate_operand" "m,r,m")))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
!    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
    "@
     fild%z1\t%1
     %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}
--- 5238,5244 ----
  	  (match_operand:SSEMODEI24 1 "nonimmediate_operand" "m,r,m")))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
!    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
    "@
     fild%z1\t%1
     %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}
***************
*** 5238,5244 ****
  	  (match_operand:SSEMODEI24 1 "memory_operand" "m,m")))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
!    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
    "@
     fild%z1\t%1
     %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
--- 5257,5263 ----
  	  (match_operand:SSEMODEI24 1 "memory_operand" "m,m")))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
!    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
    "@
     fild%z1\t%1
     %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
***************
*** 5255,5261 ****
  	  (match_operand:SI 1 "nonimmediate_operand" "r,m,!x")))
     (clobber (match_operand:SI 2 "memory_operand" "=m,X,m"))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
    "#"
    [(set_attr "type" "sseicvt")
     (set_attr "mode" "<MODE>,<MODE>,<ssevecmode>")
--- 5274,5280 ----
  	  (match_operand:SI 1 "nonimmediate_operand" "r,m,!x")))
     (clobber (match_operand:SI 2 "memory_operand" "=m,X,m"))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
    "#"
    [(set_attr "type" "sseicvt")
     (set_attr "mode" "<MODE>,<MODE>,<ssevecmode>")
***************
*** 5267,5273 ****
    [(set (match_operand:MODEF 0 "register_operand" "=x")
  	(float:MODEF (match_operand:SI 1 "memory_operand" "m")))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size"
    "#"
    [(set_attr "type" "sseicvt")
     (set_attr "mode" "<MODE>")
--- 5286,5292 ----
    [(set (match_operand:MODEF 0 "register_operand" "=x")
  	(float:MODEF (match_operand:SI 1 "memory_operand" "m")))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
    "#"
    [(set_attr "type" "sseicvt")
     (set_attr "mode" "<MODE>")
***************
*** 5280,5286 ****
  	(float:MODEF (match_operand:SI 1 "register_operand" "")))
     (clobber (match_operand:SI 2 "memory_operand" ""))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
--- 5299,5305 ----
  	(float:MODEF (match_operand:SI 1 "register_operand" "")))
     (clobber (match_operand:SI 2 "memory_operand" ""))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
***************
*** 5321,5327 ****
  	(float:MODEF (match_operand:SI 1 "memory_operand" "")))
     (clobber (match_operand:SI 2 "memory_operand" ""))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
--- 5340,5346 ----
  	(float:MODEF (match_operand:SI 1 "memory_operand" "")))
     (clobber (match_operand:SI 2 "memory_operand" ""))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
***************
*** 5343,5349 ****
    [(set (match_operand:MODEF 0 "register_operand" "")
  	(float:MODEF (match_operand:SI 1 "register_operand" "")))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
--- 5362,5368 ----
    [(set (match_operand:MODEF 0 "register_operand" "")
  	(float:MODEF (match_operand:SI 1 "register_operand" "")))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
***************
*** 5375,5381 ****
    [(set (match_operand:MODEF 0 "register_operand" "")
  	(float:MODEF (match_operand:SI 1 "memory_operand" "")))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && !optimize_size
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
--- 5394,5400 ----
    [(set (match_operand:MODEF 0 "register_operand" "")
  	(float:MODEF (match_operand:SI 1 "memory_operand" "")))]
    "TARGET_SSE2 && TARGET_SSE_MATH
!    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
***************
*** 5413,5419 ****
  	  (match_operand:SSEMODEI24 1 "nonimmediate_operand" "r,m")))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
!    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
    "%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
    [(set_attr "type" "sseicvt")
     (set_attr "prefix" "maybe_vex")
--- 5432,5438 ----
  	  (match_operand:SSEMODEI24 1 "nonimmediate_operand" "r,m")))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
!    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
    "%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
    [(set_attr "type" "sseicvt")
     (set_attr "prefix" "maybe_vex")
***************
*** 5428,5434 ****
     (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
!    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_size)
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
--- 5447,5453 ----
     (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
!    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
***************
*** 5442,5448 ****
  	  (match_operand:SSEMODEI24 1 "memory_operand" "m")))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
!    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size)"
    "%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
    [(set_attr "type" "sseicvt")
     (set_attr "prefix" "maybe_vex")
--- 5461,5467 ----
  	  (match_operand:SSEMODEI24 1 "memory_operand" "m")))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
!    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
    "%vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
    [(set_attr "type" "sseicvt")
     (set_attr "prefix" "maybe_vex")
***************
*** 5457,5463 ****
     (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
!    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_size)
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
--- 5476,5482 ----
     (clobber (match_operand:SSEMODEI24 2 "memory_operand" ""))]
    "(<SSEMODEI24:MODE>mode != DImode || TARGET_64BIT)
     && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
!    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))
     && reload_completed
     && (SSE_REG_P (operands[0])
         || (GET_CODE (operands[0]) == SUBREG
***************
*** 5535,5541 ****
     (clobber (match_scratch:V4SI 4 "=X,x"))
     (clobber (match_operand:DI 2 "memory_operand" "=X,m"))]
    "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
!    && !TARGET_64BIT && !optimize_size"
    "#"
    [(set_attr "type" "multi")
     (set_attr "mode" "<X87MODEF:MODE>")
--- 5554,5560 ----
     (clobber (match_scratch:V4SI 4 "=X,x"))
     (clobber (match_operand:DI 2 "memory_operand" "=X,m"))]
    "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
!    && !TARGET_64BIT && optimize_function_for_speed_p (cfun)"
    "#"
    [(set_attr "type" "multi")
     (set_attr "mode" "<X87MODEF:MODE>")
***************
*** 5549,5555 ****
     (clobber (match_scratch:V4SI 4 ""))
     (clobber (match_operand:DI 2 "memory_operand" ""))]
    "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
!    && !TARGET_64BIT && !optimize_size
     && reload_completed
     && FP_REG_P (operands[0])"
    [(set (match_dup 2) (match_dup 3))
--- 5568,5574 ----
     (clobber (match_scratch:V4SI 4 ""))
     (clobber (match_operand:DI 2 "memory_operand" ""))]
    "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
!    && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
     && reload_completed
     && FP_REG_P (operands[0])"
    [(set (match_dup 2) (match_dup 3))
***************
*** 5573,5579 ****
     (clobber (match_scratch:V4SI 4 ""))
     (clobber (match_operand:DI 2 "memory_operand" ""))]
    "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
!    && !TARGET_64BIT && !optimize_size
     && reload_completed
     && FP_REG_P (operands[0])"
    [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]
--- 5592,5598 ----
     (clobber (match_scratch:V4SI 4 ""))
     (clobber (match_operand:DI 2 "memory_operand" ""))]
    "TARGET_80387 && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES
!    && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
     && reload_completed
     && FP_REG_P (operands[0])"
    [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]
***************
*** 5938,5944 ****
  	      (match_operand 3 "immediate_operand" "i")))]
    "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
      || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
!    && (!TARGET_PARTIAL_REG_STALL || optimize_size)
     && GET_MODE (operands[0]) == GET_MODE (operands[1])
     && GET_MODE (operands[0]) == GET_MODE (operands[2])
     && (GET_MODE (operands[0]) == GET_MODE (operands[3])
--- 5957,5963 ----
  	      (match_operand 3 "immediate_operand" "i")))]
    "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
      || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
!    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && GET_MODE (operands[0]) == GET_MODE (operands[1])
     && GET_MODE (operands[0]) == GET_MODE (operands[2])
     && (GET_MODE (operands[0]) == GET_MODE (operands[3])
***************
*** 5990,5996 ****
  	      (match_operand 3 "nonmemory_operand" "ri")))]
    "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
      || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
!    && (!TARGET_PARTIAL_REG_STALL || optimize_size)
     && GET_MODE (operands[0]) == GET_MODE (operands[1])
     && (GET_MODE (operands[0]) == GET_MODE (operands[3])
         || GET_MODE (operands[3]) == VOIDmode)"
--- 6009,6015 ----
  	      (match_operand 3 "nonmemory_operand" "ri")))]
    "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
      || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
!    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && GET_MODE (operands[0]) == GET_MODE (operands[1])
     && (GET_MODE (operands[0]) == GET_MODE (operands[3])
         || GET_MODE (operands[3]) == VOIDmode)"
***************
*** 6040,6046 ****
  	      (match_operand 4 "immediate_operand" "i")))]
    "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
      || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
!    && (!TARGET_PARTIAL_REG_STALL || optimize_size)
     && GET_MODE (operands[0]) == GET_MODE (operands[1])
     && GET_MODE (operands[0]) == GET_MODE (operands[3])"
    "#"
--- 6059,6065 ----
  	      (match_operand 4 "immediate_operand" "i")))]
    "(GET_MODE (operands[0]) == QImode || GET_MODE (operands[0]) == HImode
      || (TARGET_64BIT && GET_MODE (operands[0]) == SImode))
!    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && GET_MODE (operands[0]) == GET_MODE (operands[1])
     && GET_MODE (operands[0]) == GET_MODE (operands[3])"
    "#"
***************
*** 7137,7143 ****
  	(plus:QI (match_dup 0)
  		 (match_operand:QI 1 "general_operand" "qn,qnm")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  {
    switch (get_attr_type (insn))
--- 7156,7162 ----
  	(plus:QI (match_dup 0)
  		 (match_operand:QI 1 "general_operand" "qn,qnm")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
  {
    switch (get_attr_type (insn))
***************
*** 7750,7756 ****
  	(minus:QI (match_dup 0)
  		  (match_operand:QI 1 "general_operand" "qn,qm")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "sub{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
--- 7769,7775 ----
  	(minus:QI (match_dup 0)
  		  (match_operand:QI 1 "general_operand" "qn,qm")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "sub{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
***************
*** 8432,8438 ****
     (set (match_operand:DI 1 "register_operand" "=&d,&d")
  	(mod:DI (match_dup 2) (match_dup 3)))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_64BIT && !optimize_size && !TARGET_USE_CLTD"
    "#"
    [(set_attr "type" "multi")])
  
--- 8451,8457 ----
     (set (match_operand:DI 1 "register_operand" "=&d,&d")
  	(mod:DI (match_dup 2) (match_dup 3)))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_64BIT && optimize_function_for_speed_p (cfun) && !TARGET_USE_CLTD"
    "#"
    [(set_attr "type" "multi")])
  
***************
*** 8443,8449 ****
     (set (match_operand:DI 1 "register_operand" "=&d")
  	(mod:DI (match_dup 2) (match_dup 3)))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_64BIT && (optimize_size || TARGET_USE_CLTD)"
    "#"
    [(set_attr "type" "multi")])
  
--- 8462,8468 ----
     (set (match_operand:DI 1 "register_operand" "=&d")
  	(mod:DI (match_dup 2) (match_dup 3)))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_64BIT && (optimize_function_for_size_p (cfun) || TARGET_USE_CLTD)"
    "#"
    [(set_attr "type" "multi")])
  
***************
*** 8479,8485 ****
  	      (clobber (reg:CC FLAGS_REG))])]
  {
    /* Avoid use of cltd in favor of a mov+shift.  */
!   if (!TARGET_USE_CLTD && !optimize_size)
      {
        if (true_regnum (operands[1]))
          emit_move_insn (operands[0], operands[1]);
--- 8498,8504 ----
  	      (clobber (reg:CC FLAGS_REG))])]
  {
    /* Avoid use of cltd in favor of a mov+shift.  */
!   if (!TARGET_USE_CLTD && optimize_function_for_speed_p (cfun))
      {
        if (true_regnum (operands[1]))
          emit_move_insn (operands[0], operands[1]);
***************
*** 8515,8521 ****
     (set (match_operand:SI 1 "register_operand" "=&d,&d")
  	(mod:SI (match_dup 2) (match_dup 3)))
     (clobber (reg:CC FLAGS_REG))]
!   "!optimize_size && !TARGET_USE_CLTD"
    "#"
    [(set_attr "type" "multi")])
  
--- 8534,8540 ----
     (set (match_operand:SI 1 "register_operand" "=&d,&d")
  	(mod:SI (match_dup 2) (match_dup 3)))
     (clobber (reg:CC FLAGS_REG))]
!   "optimize_function_for_speed_p (cfun) && !TARGET_USE_CLTD"
    "#"
    [(set_attr "type" "multi")])
  
***************
*** 8526,8532 ****
     (set (match_operand:SI 1 "register_operand" "=&d")
  	(mod:SI (match_dup 2) (match_dup 3)))
     (clobber (reg:CC FLAGS_REG))]
!   "optimize_size || TARGET_USE_CLTD"
    "#"
    [(set_attr "type" "multi")])
  
--- 8545,8551 ----
     (set (match_operand:SI 1 "register_operand" "=&d")
  	(mod:SI (match_dup 2) (match_dup 3)))
     (clobber (reg:CC FLAGS_REG))]
!   "optimize_function_for_size_p (cfun) || TARGET_USE_CLTD"
    "#"
    [(set_attr "type" "multi")])
  
***************
*** 8562,8568 ****
  	      (clobber (reg:CC FLAGS_REG))])]
  {
    /* Avoid use of cltd in favor of a mov+shift.  */
!   if (!TARGET_USE_CLTD && !optimize_size)
      {
        if (true_regnum (operands[1]))
          emit_move_insn (operands[0], operands[1]);
--- 8581,8587 ----
  	      (clobber (reg:CC FLAGS_REG))])]
  {
    /* Avoid use of cltd in favor of a mov+shift.  */
!   if (!TARGET_USE_CLTD && optimize_function_for_speed_p (cfun))
      {
        if (true_regnum (operands[1]))
          emit_move_insn (operands[0], operands[1]);
***************
*** 9165,9171 ****
  	(and (match_dup 0)
  	     (const_int -65536)))
     (clobber (reg:CC FLAGS_REG))]
!   "optimize_size || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
    [(set (strict_low_part (match_dup 1)) (const_int 0))]
    "operands[1] = gen_lowpart (HImode, operands[0]);")
  
--- 9184,9190 ----
  	(and (match_dup 0)
  	     (const_int -65536)))
     (clobber (reg:CC FLAGS_REG))]
!   "optimize_function_for_size_p (cfun) || (TARGET_FAST_PREFIX && !TARGET_PARTIAL_REG_STALL)"
    [(set (strict_low_part (match_dup 1)) (const_int 0))]
    "operands[1] = gen_lowpart (HImode, operands[0]);")
  
***************
*** 9174,9180 ****
  	(and (match_dup 0)
  	     (const_int -256)))
     (clobber (reg:CC FLAGS_REG))]
!   "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
    [(set (strict_low_part (match_dup 1)) (const_int 0))]
    "operands[1] = gen_lowpart (QImode, operands[0]);")
  
--- 9193,9199 ----
  	(and (match_dup 0)
  	     (const_int -256)))
     (clobber (reg:CC FLAGS_REG))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_REG_STALL) && reload_completed"
    [(set (strict_low_part (match_dup 1)) (const_int 0))]
    "operands[1] = gen_lowpart (QImode, operands[0]);")
  
***************
*** 9183,9189 ****
  	(and (match_dup 0)
  	     (const_int -65281)))
     (clobber (reg:CC FLAGS_REG))]
!   "(optimize_size || !TARGET_PARTIAL_REG_STALL) && reload_completed"
    [(parallel [(set (zero_extract:SI (match_dup 0)
  				    (const_int 8)
  				    (const_int 8))
--- 9202,9208 ----
  	(and (match_dup 0)
  	     (const_int -65281)))
     (clobber (reg:CC FLAGS_REG))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_REG_STALL) && reload_completed"
    [(parallel [(set (zero_extract:SI (match_dup 0)
  				    (const_int 8)
  				    (const_int 8))
***************
*** 9306,9312 ****
  	(and:QI (match_dup 0)
  		(match_operand:QI 1 "general_operand" "qn,qmn")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "and{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
--- 9325,9331 ----
  	(and:QI (match_dup 0)
  		(match_operand:QI 1 "general_operand" "qn,qmn")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "and{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
***************
*** 9358,9364 ****
  		 (const_int 0)))
     (set (strict_low_part (match_dup 0))
  	(and:QI (match_dup 0) (match_dup 1)))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && ix86_match_ccmode (insn, CCNOmode)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "and{b}\t{%1, %0|%0, %1}"
--- 9377,9383 ----
  		 (const_int 0)))
     (set (strict_low_part (match_dup 0))
  	(and:QI (match_dup 0) (match_dup 1)))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCNOmode)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "and{b}\t{%1, %0|%0, %1}"
***************
*** 9482,9488 ****
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_size)
      && !(~INTVAL (operands[2]) & ~(255 << 8))
      && GET_MODE (operands[0]) != QImode"
    [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
--- 9501,9507 ----
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
      && !(~INTVAL (operands[2]) & ~(255 << 8))
      && GET_MODE (operands[0]) != QImode"
    [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
***************
*** 9503,9509 ****
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && ANY_QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_size)
      && !(~INTVAL (operands[2]) & ~255)
      && !(INTVAL (operands[2]) & 128)
      && GET_MODE (operands[0]) != QImode"
--- 9522,9528 ----
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && ANY_QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
      && !(~INTVAL (operands[2]) & ~255)
      && !(INTVAL (operands[2]) & 128)
      && GET_MODE (operands[0]) != QImode"
***************
*** 9726,9732 ****
  	(ior:QI (match_dup 0)
  		(match_operand:QI 1 "general_operand" "qmn,qn")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "or{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
--- 9745,9751 ----
  	(ior:QI (match_dup 0)
  		(match_operand:QI 1 "general_operand" "qmn,qn")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "or{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
***************
*** 9752,9758 ****
  		 (const_int 0)))
     (set (strict_low_part (match_dup 0))
  	(ior:QI (match_dup 0) (match_dup 1)))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && ix86_match_ccmode (insn, CCNOmode)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "or{b}\t{%1, %0|%0, %1}"
--- 9771,9777 ----
  		 (const_int 0)))
     (set (strict_low_part (match_dup 0))
  	(ior:QI (match_dup 0) (match_dup 1)))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCNOmode)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "or{b}\t{%1, %0|%0, %1}"
***************
*** 9771,9777 ****
    [(set_attr "type" "alu")
     (set_attr "mode" "QI")])
  
! (define_insn "iorqi_ext_0"
    [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
  			 (const_int 8)
  			 (const_int 8))
--- 9790,9796 ----
    [(set_attr "type" "alu")
     (set_attr "mode" "QI")])
  
! (define_insn "*iorqi_ext_0"
    [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
  			 (const_int 8)
  			 (const_int 8))
***************
*** 9782,9788 ****
  	    (const_int 8))
  	  (match_operand 2 "const_int_operand" "n")))
     (clobber (reg:CC FLAGS_REG))]
!   "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
    "or{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "1")
--- 9801,9807 ----
  	    (const_int 8))
  	  (match_operand 2 "const_int_operand" "n")))
     (clobber (reg:CC FLAGS_REG))]
!   "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
    "or{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "1")
***************
*** 9801,9807 ****
  	    (match_operand:QI 2 "general_operand" "Qm"))))
     (clobber (reg:CC FLAGS_REG))]
    "!TARGET_64BIT
!    && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
    "or{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
--- 9820,9826 ----
  	    (match_operand:QI 2 "general_operand" "Qm"))))
     (clobber (reg:CC FLAGS_REG))]
    "!TARGET_64BIT
!    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
    "or{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
***************
*** 9820,9826 ****
  	    (match_operand 2 "ext_register_operand" "Q"))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
    "or{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
--- 9839,9845 ----
  	    (match_operand 2 "ext_register_operand" "Q"))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
    "or{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
***************
*** 9838,9844 ****
  	  		   (const_int 8)
  			   (const_int 8))))
     (clobber (reg:CC FLAGS_REG))]
!   "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
    "ior{b}\t{%h2, %h0|%h0, %h2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
--- 9857,9863 ----
  	  		   (const_int 8)
  			   (const_int 8))))
     (clobber (reg:CC FLAGS_REG))]
!   "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
    "ior{b}\t{%h2, %h0|%h0, %h2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
***************
*** 9851,9857 ****
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_size)
      && !(INTVAL (operands[2]) & ~(255 << 8))
      && GET_MODE (operands[0]) != QImode"
    [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
--- 9870,9876 ----
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
      && !(INTVAL (operands[2]) & ~(255 << 8))
      && GET_MODE (operands[0]) != QImode"
    [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
***************
*** 9872,9878 ****
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && ANY_QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_size)
      && !(INTVAL (operands[2]) & ~255)
      && (INTVAL (operands[2]) & 128)
      && GET_MODE (operands[0]) != QImode"
--- 9891,9897 ----
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && ANY_QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
      && !(INTVAL (operands[2]) & ~255)
      && (INTVAL (operands[2]) & 128)
      && GET_MODE (operands[0]) != QImode"
***************
*** 10095,10107 ****
  	(xor:QI (match_dup 0)
  		(match_operand:QI 1 "general_operand" "qn,qmn")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "xor{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
     (set_attr "mode" "QI")])
  
! (define_insn "xorqi_ext_0"
    [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
  			 (const_int 8)
  			 (const_int 8))
--- 10114,10126 ----
  	(xor:QI (match_dup 0)
  		(match_operand:QI 1 "general_operand" "qn,qmn")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "xor{b}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")
     (set_attr "mode" "QI")])
  
! (define_insn "*xorqi_ext_0"
    [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
  			 (const_int 8)
  			 (const_int 8))
***************
*** 10112,10118 ****
  	    (const_int 8))
  	  (match_operand 2 "const_int_operand" "n")))
     (clobber (reg:CC FLAGS_REG))]
!   "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
    "xor{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "1")
--- 10131,10137 ----
  	    (const_int 8))
  	  (match_operand 2 "const_int_operand" "n")))
     (clobber (reg:CC FLAGS_REG))]
!   "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
    "xor{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "1")
***************
*** 10131,10137 ****
  	    (match_operand:QI 2 "general_operand" "Qm"))))
     (clobber (reg:CC FLAGS_REG))]
    "!TARGET_64BIT
!    && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
    "xor{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
--- 10150,10156 ----
  	    (match_operand:QI 2 "general_operand" "Qm"))))
     (clobber (reg:CC FLAGS_REG))]
    "!TARGET_64BIT
!    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
    "xor{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
***************
*** 10150,10156 ****
  	    (match_operand 2 "ext_register_operand" "Q"))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (!TARGET_PARTIAL_REG_STALL || optimize_size)"
    "xor{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
--- 10169,10175 ----
  	    (match_operand 2 "ext_register_operand" "Q"))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
    "xor{b}\t{%2, %h0|%h0, %2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
***************
*** 10168,10174 ****
  	  		   (const_int 8)
  			   (const_int 8))))
     (clobber (reg:CC FLAGS_REG))]
!   "(!TARGET_PARTIAL_REG_STALL || optimize_size)"
    "xor{b}\t{%h2, %h0|%h0, %h2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
--- 10187,10193 ----
  	  		   (const_int 8)
  			   (const_int 8))))
     (clobber (reg:CC FLAGS_REG))]
!   "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))"
    "xor{b}\t{%h2, %h0|%h0, %h2}"
    [(set_attr "type" "alu")
     (set_attr "length_immediate" "0")
***************
*** 10195,10201 ****
  		 (const_int 0)))
     (set (strict_low_part (match_dup 0))
  	(xor:QI (match_dup 0) (match_dup 1)))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && ix86_match_ccmode (insn, CCNOmode)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "xor{b}\t{%1, %0|%0, %1}"
--- 10214,10220 ----
  		 (const_int 0)))
     (set (strict_low_part (match_dup 0))
  	(xor:QI (match_dup 0) (match_dup 1)))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCNOmode)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "xor{b}\t{%1, %0|%0, %1}"
***************
*** 10284,10290 ****
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_size)
      && !(INTVAL (operands[2]) & ~(255 << 8))
      && GET_MODE (operands[0]) != QImode"
    [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
--- 10303,10309 ----
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
      && !(INTVAL (operands[2]) & ~(255 << 8))
      && GET_MODE (operands[0]) != QImode"
    [(parallel [(set (zero_extract:SI (match_dup 0) (const_int 8) (const_int 8))
***************
*** 10305,10311 ****
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && ANY_QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_size)
      && !(INTVAL (operands[2]) & ~255)
      && (INTVAL (operands[2]) & 128)
      && GET_MODE (operands[0]) != QImode"
--- 10324,10330 ----
     (clobber (reg:CC FLAGS_REG))]
     "reload_completed
      && ANY_QI_REG_P (operands[0])
!     && (!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
      && !(INTVAL (operands[2]) & ~255)
      && (INTVAL (operands[2]) & 128)
      && GET_MODE (operands[0]) != QImode"
***************
*** 11193,11199 ****
        if (REG_P (operands[2]))
  	return "sal{q}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{q}\t%0";
        else
  	return "sal{q}\t{%2, %0|%0, %2}";
--- 11212,11218 ----
        if (REG_P (operands[2]))
  	return "sal{q}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{q}\t%0";
        else
  	return "sal{q}\t{%2, %0|%0, %2}";
***************
*** 11236,11242 ****
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(ashift:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (optimize_size
         || !TARGET_PARTIAL_FLAG_REG_STALL
         || (operands[2] == const1_rtx
  	   && (TARGET_SHIFT1
--- 11255,11261 ----
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(ashift:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun)
         || !TARGET_PARTIAL_FLAG_REG_STALL
         || (operands[2] == const1_rtx
  	   && (TARGET_SHIFT1
***************
*** 11254,11260 ****
        if (REG_P (operands[2]))
  	return "sal{q}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{q}\t%0";
        else
  	return "sal{q}\t{%2, %0|%0, %2}";
--- 11273,11279 ----
        if (REG_P (operands[2]))
  	return "sal{q}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{q}\t%0";
        else
  	return "sal{q}\t{%2, %0|%0, %2}";
***************
*** 11278,11284 ****
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (optimize_size
         || !TARGET_PARTIAL_FLAG_REG_STALL
         || (operands[2] == const1_rtx
  	   && (TARGET_SHIFT1
--- 11297,11303 ----
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun)
         || !TARGET_PARTIAL_FLAG_REG_STALL
         || (operands[2] == const1_rtx
  	   && (TARGET_SHIFT1
***************
*** 11296,11302 ****
        if (REG_P (operands[2]))
  	return "sal{q}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{q}\t%0";
        else
  	return "sal{q}\t{%2, %0|%0, %2}";
--- 11315,11321 ----
        if (REG_P (operands[2]))
  	return "sal{q}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{q}\t%0";
        else
  	return "sal{q}\t{%2, %0|%0, %2}";
***************
*** 11433,11439 ****
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{l}\t%0";
        else
  	return "sal{l}\t{%2, %0|%0, %2}";
--- 11452,11458 ----
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{l}\t%0";
        else
  	return "sal{l}\t{%2, %0|%0, %2}";
***************
*** 11518,11524 ****
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %k0|%k0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{l}\t%k0";
        else
  	return "sal{l}\t{%2, %k0|%k0, %2}";
--- 11537,11543 ----
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %k0|%k0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{l}\t%k0";
        else
  	return "sal{l}\t{%2, %k0|%k0, %2}";
***************
*** 11562,11568 ****
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(ashift:SI (match_dup 1) (match_dup 2)))]
!    "(optimize_size
       || !TARGET_PARTIAL_FLAG_REG_STALL
       || (operands[2] == const1_rtx
  	 && (TARGET_SHIFT1
--- 11581,11587 ----
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(ashift:SI (match_dup 1) (match_dup 2)))]
!    "(optimize_function_for_size_p (cfun)
       || !TARGET_PARTIAL_FLAG_REG_STALL
       || (operands[2] == const1_rtx
  	 && (TARGET_SHIFT1
***************
*** 11580,11586 ****
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{l}\t%0";
        else
  	return "sal{l}\t{%2, %0|%0, %2}";
--- 11599,11605 ----
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{l}\t%0";
        else
  	return "sal{l}\t{%2, %0|%0, %2}";
***************
*** 11603,11609 ****
  		     (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(optimize_size
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
--- 11622,11628 ----
  		     (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(optimize_function_for_size_p (cfun)
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
***************
*** 11621,11627 ****
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{l}\t%0";
        else
  	return "sal{l}\t{%2, %0|%0, %2}";
--- 11640,11646 ----
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{l}\t%0";
        else
  	return "sal{l}\t{%2, %0|%0, %2}";
***************
*** 11646,11652 ****
     (set (match_operand:DI 0 "register_operand" "=r")
  	(zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
    "TARGET_64BIT
!    && (optimize_size
         || !TARGET_PARTIAL_FLAG_REG_STALL
         || (operands[2] == const1_rtx
  	   && (TARGET_SHIFT1
--- 11665,11671 ----
     (set (match_operand:DI 0 "register_operand" "=r")
  	(zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun)
         || !TARGET_PARTIAL_FLAG_REG_STALL
         || (operands[2] == const1_rtx
  	   && (TARGET_SHIFT1
***************
*** 11664,11670 ****
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %k0|%k0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{l}\t%k0";
        else
  	return "sal{l}\t{%2, %k0|%k0, %2}";
--- 11683,11689 ----
        if (REG_P (operands[2]))
  	return "sal{l}\t{%b2, %k0|%k0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{l}\t%k0";
        else
  	return "sal{l}\t{%2, %k0|%k0, %2}";
***************
*** 11706,11712 ****
        if (REG_P (operands[2]))
  	return "sal{w}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{w}\t%0";
        else
  	return "sal{w}\t{%2, %0|%0, %2}";
--- 11725,11731 ----
        if (REG_P (operands[2]))
  	return "sal{w}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{w}\t%0";
        else
  	return "sal{w}\t{%2, %0|%0, %2}";
***************
*** 11742,11748 ****
        if (REG_P (operands[2]))
  	return "sal{w}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{w}\t%0";
        else
  	return "sal{w}\t{%2, %0|%0, %2}";
--- 11761,11767 ----
        if (REG_P (operands[2]))
  	return "sal{w}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{w}\t%0";
        else
  	return "sal{w}\t{%2, %0|%0, %2}";
***************
*** 11769,11775 ****
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(ashift:HI (match_dup 1) (match_dup 2)))]
!   "(optimize_size
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
--- 11788,11794 ----
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(ashift:HI (match_dup 1) (match_dup 2)))]
!   "(optimize_function_for_size_p (cfun)
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
***************
*** 11787,11793 ****
        if (REG_P (operands[2]))
  	return "sal{w}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{w}\t%0";
        else
  	return "sal{w}\t{%2, %0|%0, %2}";
--- 11806,11812 ----
        if (REG_P (operands[2]))
  	return "sal{w}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{w}\t%0";
        else
  	return "sal{w}\t{%2, %0|%0, %2}";
***************
*** 11810,11816 ****
  		     (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(optimize_size
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
--- 11829,11835 ----
  		     (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(optimize_function_for_size_p (cfun)
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
***************
*** 11828,11834 ****
        if (REG_P (operands[2]))
  	return "sal{w}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{w}\t%0";
        else
  	return "sal{w}\t{%2, %0|%0, %2}";
--- 11847,11853 ----
        if (REG_P (operands[2]))
  	return "sal{w}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{w}\t%0";
        else
  	return "sal{w}\t{%2, %0|%0, %2}";
***************
*** 11881,11887 ****
  	    return "sal{b}\t{%b2, %0|%0, %b2}";
  	}
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	{
  	  if (get_attr_mode (insn) == MODE_SI)
  	    return "sal{l}\t%0";
--- 11900,11906 ----
  	    return "sal{b}\t{%b2, %0|%0, %b2}";
  	}
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	{
  	  if (get_attr_mode (insn) == MODE_SI)
  	    return "sal{l}\t%0";
***************
*** 11935,11941 ****
  	    return "sal{b}\t{%b2, %0|%0, %b2}";
  	}
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	{
  	  if (get_attr_mode (insn) == MODE_SI)
  	    return "sal{l}\t%0";
--- 11954,11960 ----
  	    return "sal{b}\t{%b2, %0|%0, %b2}";
  	}
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	{
  	  if (get_attr_mode (insn) == MODE_SI)
  	    return "sal{l}\t%0";
***************
*** 11972,11978 ****
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(ashift:QI (match_dup 1) (match_dup 2)))]
!   "(optimize_size
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
--- 11991,11997 ----
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(ashift:QI (match_dup 1) (match_dup 2)))]
!   "(optimize_function_for_size_p (cfun)
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
***************
*** 11990,11996 ****
        if (REG_P (operands[2]))
  	return "sal{b}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{b}\t%0";
        else
  	return "sal{b}\t{%2, %0|%0, %2}";
--- 12009,12015 ----
        if (REG_P (operands[2]))
  	return "sal{b}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{b}\t%0";
        else
  	return "sal{b}\t{%2, %0|%0, %2}";
***************
*** 12013,12019 ****
  		     (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(optimize_size
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
--- 12032,12038 ----
  		     (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(optimize_function_for_size_p (cfun)
      || !TARGET_PARTIAL_FLAG_REG_STALL
      || (operands[2] == const1_rtx
  	&& (TARGET_SHIFT1
***************
*** 12031,12037 ****
        if (REG_P (operands[2]))
  	return "sal{b}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_size))
  	return "sal{b}\t%0";
        else
  	return "sal{b}\t{%2, %0|%0, %2}";
--- 12050,12056 ----
        if (REG_P (operands[2]))
  	return "sal{b}\t{%b2, %0|%0, %b2}";
        else if (operands[2] == const1_rtx
! 	       && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
  	return "sal{b}\t%0";
        else
  	return "sal{b}\t{%2, %0|%0, %2}";
***************
*** 12142,12148 ****
  		     (match_operand:DI 2 "const_int_operand" "i,i")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT && INTVAL (operands[2]) == 63
!    && (TARGET_USE_CLTD || optimize_size)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "@
     {cqto|cqo}
--- 12161,12167 ----
  		     (match_operand:DI 2 "const_int_operand" "i,i")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT && INTVAL (operands[2]) == 63
!    && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "@
     {cqto|cqo}
***************
*** 12159,12165 ****
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t%0"
    [(set_attr "type" "ishift")
--- 12178,12184 ----
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t%0"
    [(set_attr "type" "ishift")
***************
*** 12192,12198 ****
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t%0"
--- 12211,12217 ----
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t%0"
***************
*** 12210,12216 ****
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t%0"
--- 12229,12235 ----
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t%0"
***************
*** 12229,12235 ****
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t{%2, %0|%0, %2}"
--- 12248,12254 ----
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t{%2, %0|%0, %2}"
***************
*** 12244,12250 ****
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t{%2, %0|%0, %2}"
--- 12263,12269 ----
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
    "sar{q}\t{%2, %0|%0, %2}"
***************
*** 12326,12337 ****
    DONE;
  })
  
! (define_insn "ashrsi3_31"
    [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
  	(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
  		     (match_operand:SI 2 "const_int_operand" "i,i")))
     (clobber (reg:CC FLAGS_REG))]
!   "INTVAL (operands[2]) == 31 && (TARGET_USE_CLTD || optimize_size)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "@
     {cltd|cdq}
--- 12345,12364 ----
    DONE;
  })
  
! (define_expand "ashrsi3_31"
!   [(parallel [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
! 	           (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
! 		                (match_operand:SI 2 "const_int_operand" "i,i")))
!               (clobber (reg:CC FLAGS_REG))])]
!   "")
! 
! (define_insn "*ashrsi3_31"
    [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,rm")
  	(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "*a,0")
  		     (match_operand:SI 2 "const_int_operand" "i,i")))
     (clobber (reg:CC FLAGS_REG))]
!   "INTVAL (operands[2]) == 31
!    && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "@
     {cltd|cdq}
***************
*** 12347,12353 ****
  	(zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
  				     (match_operand:SI 2 "const_int_operand" "i,i"))))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_64BIT && (TARGET_USE_CLTD || optimize_size)
     && INTVAL (operands[2]) == 31
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "@
--- 12374,12380 ----
  	(zero_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "*a,0")
  				     (match_operand:SI 2 "const_int_operand" "i,i"))))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_64BIT && (TARGET_USE_CLTD || optimize_function_for_size_p (cfun))
     && INTVAL (operands[2]) == 31
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "@
***************
*** 12371,12377 ****
  	(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%0"
    [(set_attr "type" "ishift")
--- 12398,12404 ----
  	(ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%0"
    [(set_attr "type" "ishift")
***************
*** 12386,12392 ****
  				     (match_operand:QI 2 "const1_operand" ""))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%k0"
    [(set_attr "type" "ishift")
--- 12413,12419 ----
  				     (match_operand:QI 2 "const1_operand" ""))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%k0"
    [(set_attr "type" "ishift")
***************
*** 12427,12433 ****
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%0"
--- 12454,12460 ----
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%0"
***************
*** 12444,12450 ****
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%0"
--- 12471,12477 ----
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%0"
***************
*** 12460,12466 ****
     (set (match_operand:DI 0 "register_operand" "=r")
  	(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%k0"
--- 12487,12493 ----
     (set (match_operand:DI 0 "register_operand" "=r")
  	(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t%k0"
***************
*** 12478,12484 ****
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t{%2, %0|%0, %2}"
--- 12505,12511 ----
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t{%2, %0|%0, %2}"
***************
*** 12492,12498 ****
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t{%2, %0|%0, %2}"
--- 12519,12525 ----
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t{%2, %0|%0, %2}"
***************
*** 12508,12514 ****
     (set (match_operand:DI 0 "register_operand" "=r")
  	(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
    "TARGET_64BIT
!    && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t{%2, %k0|%k0, %2}"
--- 12535,12541 ----
     (set (match_operand:DI 0 "register_operand" "=r")
  	(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
    "sar{l}\t{%2, %k0|%k0, %2}"
***************
*** 12527,12533 ****
  	(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t%0"
    [(set_attr "type" "ishift")
--- 12554,12560 ----
  	(ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t%0"
    [(set_attr "type" "ishift")
***************
*** 12559,12565 ****
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:HI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t%0"
--- 12586,12592 ----
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:HI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t%0"
***************
*** 12576,12582 ****
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t%0"
--- 12603,12609 ----
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t%0"
***************
*** 12594,12600 ****
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:HI (match_dup 1) (match_dup 2)))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t{%2, %0|%0, %2}"
--- 12621,12627 ----
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(ashiftrt:HI (match_dup 1) (match_dup 2)))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t{%2, %0|%0, %2}"
***************
*** 12608,12614 ****
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t{%2, %0|%0, %2}"
--- 12635,12641 ----
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
    "sar{w}\t{%2, %0|%0, %2}"
***************
*** 12627,12633 ****
  	(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t%0"
    [(set_attr "type" "ishift")
--- 12654,12660 ----
  	(ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t%0"
    [(set_attr "type" "ishift")
***************
*** 12641,12648 ****
  	(ashiftrt:QI (match_dup 0)
  		     (match_operand:QI 1 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t%0"
    [(set_attr "type" "ishift1")
--- 12668,12675 ----
  	(ashiftrt:QI (match_dup 0)
  		     (match_operand:QI 1 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t%0"
    [(set_attr "type" "ishift1")
***************
*** 12668,12674 ****
  	(ashiftrt:QI (match_dup 0)
  		     (match_operand:QI 1 "nonmemory_operand" "I,c")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "@
     sar{b}\t{%1, %0|%0, %1}
--- 12695,12701 ----
  	(ashiftrt:QI (match_dup 0)
  		     (match_operand:QI 1 "nonmemory_operand" "I,c")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "@
     sar{b}\t{%1, %0|%0, %1}
***************
*** 12687,12693 ****
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(ashiftrt:QI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t%0"
--- 12714,12720 ----
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(ashiftrt:QI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t%0"
***************
*** 12704,12710 ****
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t%0"
--- 12731,12737 ----
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t%0"
***************
*** 12722,12728 ****
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(ashiftrt:QI (match_dup 1) (match_dup 2)))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t{%2, %0|%0, %2}"
--- 12749,12755 ----
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(ashiftrt:QI (match_dup 1) (match_dup 2)))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t{%2, %0|%0, %2}"
***************
*** 12736,12742 ****
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t{%2, %0|%0, %2}"
--- 12763,12769 ----
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
    "sar{b}\t{%2, %0|%0, %2}"
***************
*** 12827,12833 ****
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t%0"
    [(set_attr "type" "ishift")
--- 12854,12860 ----
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t%0"
    [(set_attr "type" "ishift")
***************
*** 12860,12866 ****
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t%0"
--- 12887,12893 ----
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t%0"
***************
*** 12878,12884 ****
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t%0"
--- 12905,12911 ----
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t%0"
***************
*** 12897,12903 ****
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t{%2, %0|%0, %2}"
--- 12924,12930 ----
     (set (match_operand:DI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:DI (match_dup 1) (match_dup 2)))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t{%2, %0|%0, %2}"
***************
*** 12912,12918 ****
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t{%2, %0|%0, %2}"
--- 12939,12945 ----
  	  (const_int 0)))
     (clobber (match_scratch:DI 0 "=r"))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{q}\t{%2, %0|%0, %2}"
***************
*** 12964,12970 ****
  	(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%0"
    [(set_attr "type" "ishift")
--- 12991,12997 ----
  	(lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%0"
    [(set_attr "type" "ishift")
***************
*** 12979,12985 ****
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%k0"
    [(set_attr "type" "ishift")
--- 13006,13012 ----
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%k0"
    [(set_attr "type" "ishift")
***************
*** 13021,13027 ****
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%0"
--- 13048,13054 ----
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%0"
***************
*** 13038,13044 ****
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%0"
--- 13065,13071 ----
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%0"
***************
*** 13054,13060 ****
     (set (match_operand:DI 0 "register_operand" "=r")
  	(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%k0"
--- 13081,13087 ----
     (set (match_operand:DI 0 "register_operand" "=r")
  	(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t%k0"
***************
*** 13072,13078 ****
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t{%2, %0|%0, %2}"
--- 13099,13105 ----
  	  (const_int 0)))
     (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t{%2, %0|%0, %2}"
***************
*** 13086,13092 ****
  		     (match_operand:QI 2 "const_1_to_31_operand" "I"))
          (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t{%2, %0|%0, %2}"
--- 13113,13119 ----
  		     (match_operand:QI 2 "const_1_to_31_operand" "I"))
          (const_int 0)))
     (clobber (match_scratch:SI 0 "=r"))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t{%2, %0|%0, %2}"
***************
*** 13102,13108 ****
     (set (match_operand:DI 0 "register_operand" "=r")
  	(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
    "TARGET_64BIT
!    && (optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t{%2, %k0|%k0, %2}"
--- 13129,13135 ----
     (set (match_operand:DI 0 "register_operand" "=r")
  	(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
    "TARGET_64BIT
!    && (optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{l}\t{%2, %k0|%k0, %2}"
***************
*** 13121,13127 ****
  	(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t%0"
    [(set_attr "type" "ishift")
--- 13148,13154 ----
  	(lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t%0"
    [(set_attr "type" "ishift")
***************
*** 13153,13159 ****
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:HI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t%0"
--- 13180,13186 ----
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:HI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t%0"
***************
*** 13170,13176 ****
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t%0"
--- 13197,13203 ----
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t%0"
***************
*** 13188,13194 ****
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:HI (match_dup 1) (match_dup 2)))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t{%2, %0|%0, %2}"
--- 13215,13221 ----
  	  (const_int 0)))
     (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
  	(lshiftrt:HI (match_dup 1) (match_dup 2)))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t{%2, %0|%0, %2}"
***************
*** 13202,13208 ****
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t{%2, %0|%0, %2}"
--- 13229,13235 ----
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:HI 0 "=r"))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
    "shr{w}\t{%2, %0|%0, %2}"
***************
*** 13221,13227 ****
  	(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t%0"
    [(set_attr "type" "ishift")
--- 13248,13254 ----
  	(lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t%0"
    [(set_attr "type" "ishift")
***************
*** 13235,13242 ****
  	(lshiftrt:QI (match_dup 0)
  		     (match_operand:QI 1 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
!    && (TARGET_SHIFT1 || optimize_size)"
    "shr{b}\t%0"
    [(set_attr "type" "ishift1")
     (set (attr "length")
--- 13262,13269 ----
  	(lshiftrt:QI (match_dup 0)
  		     (match_operand:QI 1 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))"
    "shr{b}\t%0"
    [(set_attr "type" "ishift1")
     (set (attr "length")
***************
*** 13261,13267 ****
  	(lshiftrt:QI (match_dup 0)
  		     (match_operand:QI 1 "nonmemory_operand" "I,c")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "@
     shr{b}\t{%1, %0|%0, %1}
--- 13288,13294 ----
  	(lshiftrt:QI (match_dup 0)
  		     (match_operand:QI 1 "nonmemory_operand" "I,c")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "@
     shr{b}\t{%1, %0|%0, %1}
***************
*** 13280,13286 ****
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(lshiftrt:QI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t%0"
--- 13307,13313 ----
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(lshiftrt:QI (match_dup 1) (match_dup 2)))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t%0"
***************
*** 13297,13303 ****
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t%0"
--- 13324,13330 ----
  		       (match_operand:QI 2 "const1_operand" ""))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t%0"
***************
*** 13315,13321 ****
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(lshiftrt:QI (match_dup 1) (match_dup 2)))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t{%2, %0|%0, %2}"
--- 13342,13348 ----
  	  (const_int 0)))
     (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
  	(lshiftrt:QI (match_dup 1) (match_dup 2)))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t{%2, %0|%0, %2}"
***************
*** 13329,13335 ****
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(optimize_size || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t{%2, %0|%0, %2}"
--- 13356,13362 ----
  		       (match_operand:QI 2 "const_1_to_31_operand" "I"))
  	  (const_int 0)))
     (clobber (match_scratch:QI 0 "=q"))]
!   "(optimize_function_for_size_p (cfun) || !TARGET_PARTIAL_FLAG_REG_STALL)
     && ix86_match_ccmode (insn, CCGOCmode)
     && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
    "shr{b}\t{%2, %0|%0, %2}"
***************
*** 13387,13393 ****
  		   (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATE, DImode, operands)"
    "rol{q}\t%0"
    [(set_attr "type" "rotate")
--- 13414,13420 ----
  		   (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATE, DImode, operands)"
    "rol{q}\t%0"
    [(set_attr "type" "rotate")
***************
*** 13420,13426 ****
  	(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
  		   (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATE, SImode, operands)"
    "rol{l}\t%0"
    [(set_attr "type" "rotate")
--- 13447,13453 ----
  	(rotate:SI (match_operand:SI 1 "nonimmediate_operand" "0")
  		   (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATE, SImode, operands)"
    "rol{l}\t%0"
    [(set_attr "type" "rotate")
***************
*** 13436,13442 ****
  		     (match_operand:QI 2 "const1_operand" ""))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATE, SImode, operands)"
    "rol{l}\t%k0"
    [(set_attr "type" "rotate")
--- 13463,13469 ----
  		     (match_operand:QI 2 "const1_operand" ""))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATE, SImode, operands)"
    "rol{l}\t%k0"
    [(set_attr "type" "rotate")
***************
*** 13479,13485 ****
  	(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
  		   (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATE, HImode, operands)"
    "rol{w}\t%0"
    [(set_attr "type" "rotate")
--- 13506,13512 ----
  	(rotate:HI (match_operand:HI 1 "nonimmediate_operand" "0")
  		   (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATE, HImode, operands)"
    "rol{w}\t%0"
    [(set_attr "type" "rotate")
***************
*** 13522,13529 ****
  	(rotate:QI (match_dup 0)
  		   (match_operand:QI 1 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
!    && (TARGET_SHIFT1 || optimize_size)"
    "rol{b}\t%0"
    [(set_attr "type" "rotate1")
     (set (attr "length")
--- 13549,13556 ----
  	(rotate:QI (match_dup 0)
  		   (match_operand:QI 1 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))"
    "rol{b}\t%0"
    [(set_attr "type" "rotate1")
     (set (attr "length")
***************
*** 13536,13542 ****
  	(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
  		   (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATE, QImode, operands)"
    "rol{b}\t%0"
    [(set_attr "type" "rotate")
--- 13563,13569 ----
  	(rotate:QI (match_operand:QI 1 "nonimmediate_operand" "0")
  		   (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATE, QImode, operands)"
    "rol{b}\t%0"
    [(set_attr "type" "rotate")
***************
*** 13550,13556 ****
  	(rotate:QI (match_dup 0)
  		   (match_operand:QI 1 "nonmemory_operand" "I,c")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "@
     rol{b}\t{%1, %0|%0, %1}
--- 13577,13583 ----
  	(rotate:QI (match_dup 0)
  		   (match_operand:QI 1 "nonmemory_operand" "I,c")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "@
     rol{b}\t{%1, %0|%0, %1}
***************
*** 13619,13625 ****
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
    "ror{q}\t%0"
    [(set_attr "type" "rotate")
--- 13646,13652 ----
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATERT, DImode, operands)"
    "ror{q}\t%0"
    [(set_attr "type" "rotate")
***************
*** 13652,13658 ****
  	(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
    "ror{l}\t%0"
    [(set_attr "type" "rotate")
--- 13679,13685 ----
  	(rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
    "ror{l}\t%0"
    [(set_attr "type" "rotate")
***************
*** 13668,13674 ****
  		       (match_operand:QI 2 "const1_operand" ""))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
    "ror{l}\t%k0"
    [(set_attr "type" "rotate")
--- 13695,13701 ----
  		       (match_operand:QI 2 "const1_operand" ""))))
     (clobber (reg:CC FLAGS_REG))]
    "TARGET_64BIT
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATERT, SImode, operands)"
    "ror{l}\t%k0"
    [(set_attr "type" "rotate")
***************
*** 13714,13720 ****
  	(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATERT, HImode, operands)"
    "ror{w}\t%0"
    [(set_attr "type" "rotate")
--- 13741,13747 ----
  	(rotatert:HI (match_operand:HI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATERT, HImode, operands)"
    "ror{w}\t%0"
    [(set_attr "type" "rotate")
***************
*** 13757,13763 ****
  	(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_size)
     && ix86_binary_operator_ok (ROTATERT, QImode, operands)"
    "ror{b}\t%0"
    [(set_attr "type" "rotate")
--- 13784,13790 ----
  	(rotatert:QI (match_operand:QI 1 "nonimmediate_operand" "0")
  		     (match_operand:QI 2 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(TARGET_SHIFT1 || optimize_function_for_size_p (cfun))
     && ix86_binary_operator_ok (ROTATERT, QImode, operands)"
    "ror{b}\t%0"
    [(set_attr "type" "rotate")
***************
*** 13771,13778 ****
  	(rotatert:QI (match_dup 0)
  		     (match_operand:QI 1 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
!    && (TARGET_SHIFT1 || optimize_size)"
    "ror{b}\t%0"
    [(set_attr "type" "rotate1")
     (set (attr "length")
--- 13798,13805 ----
  	(rotatert:QI (match_dup 0)
  		     (match_operand:QI 1 "const1_operand" "")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
!    && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun))"
    "ror{b}\t%0"
    [(set_attr "type" "rotate1")
     (set (attr "length")
***************
*** 13797,13803 ****
  	(rotatert:QI (match_dup 0)
  		     (match_operand:QI 1 "nonmemory_operand" "I,c")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_size)
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "@
     ror{b}\t{%1, %0|%0, %1}
--- 13824,13830 ----
  	(rotatert:QI (match_dup 0)
  		     (match_operand:QI 1 "nonmemory_operand" "I,c")))
     (clobber (reg:CC FLAGS_REG))]
!   "(! TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
     && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
    "@
     ror{b}\t{%1, %0|%0, %1}
***************
*** 14015,14021 ****
  	    (const_int 1)
  	    (match_operand:DI 1 "nonmemory_operand" "rN"))
  	  (const_int 0)))]
!   "TARGET_64BIT && (TARGET_USE_BT || optimize_size)"
    "bt{q}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")])
  
--- 14042,14048 ----
  	    (const_int 1)
  	    (match_operand:DI 1 "nonmemory_operand" "rN"))
  	  (const_int 0)))]
!   "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
    "bt{q}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")])
  
***************
*** 14027,14033 ****
  	    (const_int 1)
  	    (match_operand:SI 1 "nonmemory_operand" "rN"))
  	  (const_int 0)))]
!   "TARGET_USE_BT || optimize_size"
    "bt{l}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")])
  
--- 14054,14060 ----
  	    (const_int 1)
  	    (match_operand:SI 1 "nonmemory_operand" "rN"))
  	  (const_int 0)))]
!   "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
    "bt{l}\t{%1, %0|%0, %1}"
    [(set_attr "type" "alu1")])
  
***************
*** 14372,14378 ****
  			 (const_int 0)])
  		      (label_ref (match_operand 3 "" ""))
  		      (pc)))]
!   "TARGET_64BIT && (TARGET_USE_BT || optimize_size)"
    "#"
    "&& 1"
    [(set (reg:CCC FLAGS_REG)
--- 14399,14405 ----
  			 (const_int 0)])
  		      (label_ref (match_operand 3 "" ""))
  		      (pc)))]
!   "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))"
    "#"
    "&& 1"
    [(set (reg:CCC FLAGS_REG)
***************
*** 14404,14410 ****
  			     (match_operand:SI 3 "const_int_operand" "n")))])
  		      (label_ref (match_operand 4 "" ""))
  		      (pc)))]
!   "TARGET_64BIT && (TARGET_USE_BT || optimize_size)
     && (INTVAL (operands[3]) & 0x3f) == 0x3f"
    "#"
    "&& 1"
--- 14431,14437 ----
  			     (match_operand:SI 3 "const_int_operand" "n")))])
  		      (label_ref (match_operand 4 "" ""))
  		      (pc)))]
!   "TARGET_64BIT && (TARGET_USE_BT || optimize_function_for_size_p (cfun))
     && (INTVAL (operands[3]) & 0x3f) == 0x3f"
    "#"
    "&& 1"
***************
*** 14436,14442 ****
  			 (const_int 0)])
  		      (label_ref (match_operand 3 "" ""))
  		      (pc)))]
!   "TARGET_USE_BT || optimize_size"
    "#"
    "&& 1"
    [(set (reg:CCC FLAGS_REG)
--- 14463,14469 ----
  			 (const_int 0)])
  		      (label_ref (match_operand 3 "" ""))
  		      (pc)))]
!   "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
    "#"
    "&& 1"
    [(set (reg:CCC FLAGS_REG)
***************
*** 14468,14474 ****
  			     (match_operand:SI 3 "const_int_operand" "n")))])
  		      (label_ref (match_operand 4 "" ""))
  		      (pc)))]
!   "(TARGET_USE_BT || optimize_size)
     && (INTVAL (operands[3]) & 0x1f) == 0x1f"
    "#"
    "&& 1"
--- 14495,14501 ----
  			     (match_operand:SI 3 "const_int_operand" "n")))])
  		      (label_ref (match_operand 4 "" ""))
  		      (pc)))]
!   "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
     && (INTVAL (operands[3]) & 0x1f) == 0x1f"
    "#"
    "&& 1"
***************
*** 14496,14502 ****
  			 (const_int 0)])
  		      (label_ref (match_operand 3 "" ""))
  		      (pc)))]
!   "TARGET_USE_BT || optimize_size"
    "#"
    "&& 1"
    [(set (reg:CCC FLAGS_REG)
--- 14523,14529 ----
  			 (const_int 0)])
  		      (label_ref (match_operand 3 "" ""))
  		      (pc)))]
!   "TARGET_USE_BT || optimize_function_for_size_p (cfun)"
    "#"
    "&& 1"
    [(set (reg:CCC FLAGS_REG)
***************
*** 14532,14538 ****
  	     (const_int 0)])
  	  (label_ref (match_operand 4 "" ""))
  	  (pc)))]
!   "(TARGET_USE_BT || optimize_size)
     && (INTVAL (operands[3]) & 0x1f) == 0x1f"
    "#"
    "&& 1"
--- 14559,14565 ----
  	     (const_int 0)])
  	  (label_ref (match_operand 4 "" ""))
  	  (pc)))]
!   "(TARGET_USE_BT || optimize_function_for_size_p (cfun))
     && (INTVAL (operands[3]) & 0x1f) == 0x1f"
    "#"
    "&& 1"
***************
*** 14746,14752 ****
     (clobber (reg:CCFP FLAGS_REG))
     (clobber (match_scratch:HI 5 "=a,a"))]
    "X87_FLOAT_MODE_P (GET_MODE (operands[3]))
!    && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)
     && GET_MODE (operands[1]) == GET_MODE (operands[3])
     && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
     && ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
--- 14773,14779 ----
     (clobber (reg:CCFP FLAGS_REG))
     (clobber (match_scratch:HI 5 "=a,a"))]
    "X87_FLOAT_MODE_P (GET_MODE (operands[3]))
!    && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))
     && GET_MODE (operands[1]) == GET_MODE (operands[3])
     && !ix86_use_fcomi_compare (swap_condition (GET_CODE (operands[0])))
     && ix86_fp_compare_mode (swap_condition (GET_CODE (operands[0]))) == CCFPmode
***************
*** 15589,15595 ****
    [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))
  	(bswap:HI (match_dup 0)))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_USE_XCHGB || optimize_size"
    "@
      xchg{b}\t{%h0, %b0|%b0, %h0}
      rol{w}\t{$8, %0|%0, 8}"
--- 15616,15622 ----
    [(set (strict_low_part (match_operand:HI 0 "register_operand" "+Q,r"))
  	(bswap:HI (match_dup 0)))
     (clobber (reg:CC FLAGS_REG))]
!   "TARGET_USE_XCHGB || optimize_function_for_size_p (cfun)"
    "@
      xchg{b}\t{%h0, %b0|%b0, %h0}
      rol{w}\t{$8, %0|%0, 8}"
***************
*** 16444,16450 ****
  	     (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
  	   (match_operand:MODEF 2 "register_operand" "0,0")]))]
    "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
!    && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_size)"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type")
          (cond [(match_operand:MODEF 3 "mult_operator" "")
--- 16471,16477 ----
  	     (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
  	   (match_operand:MODEF 2 "register_operand" "0,0")]))]
    "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
!    && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type")
          (cond [(match_operand:MODEF 3 "mult_operator" "")
***************
*** 16463,16469 ****
  	   (float:MODEF
  	     (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
    "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
!    && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_size)"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type")
          (cond [(match_operand:MODEF 3 "mult_operator" "")
--- 16490,16496 ----
  	   (float:MODEF
  	     (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
    "TARGET_80387 && !(SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH)
!    && (TARGET_USE_<X87MODEI12:MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type")
          (cond [(match_operand:MODEF 3 "mult_operator" "")
***************
*** 16565,16571 ****
  	  [(float:XF
  	     (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
  	   (match_operand:XF 2 "register_operand" "0,0")]))]
!   "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type")
          (cond [(match_operand:XF 3 "mult_operator" "")
--- 16592,16598 ----
  	  [(float:XF
  	     (match_operand:X87MODEI12 1 "nonimmediate_operand" "m,?r"))
  	   (match_operand:XF 2 "register_operand" "0,0")]))]
!   "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type")
          (cond [(match_operand:XF 3 "mult_operator" "")
***************
*** 16583,16589 ****
  	  [(match_operand:XF 1 "register_operand" "0,0")
  	   (float:XF
  	     (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
!   "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_size)"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type")
          (cond [(match_operand:XF 3 "mult_operator" "")
--- 16610,16616 ----
  	  [(match_operand:XF 1 "register_operand" "0,0")
  	   (float:XF
  	     (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
!   "TARGET_80387 && (TARGET_USE_<MODE>MODE_FIOP || optimize_function_for_size_p (cfun))"
    "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
    [(set (attr "type")
          (cond [(match_operand:XF 3 "mult_operator" "")
***************
*** 16763,16769 ****
     || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
  {
    if (<MODE>mode == SFmode
!       && TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
        && flag_finite_math_only && !flag_trapping_math
        && flag_unsafe_math_optimizations)
      {
--- 16790,16796 ----
     || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
  {
    if (<MODE>mode == SFmode
!       && TARGET_SSE_MATH && TARGET_RECIP && !optimize_function_for_size_p (cfun)
        && flag_finite_math_only && !flag_trapping_math
        && flag_unsafe_math_optimizations)
      {
***************
*** 20313,20324 ****
     (clobber (reg:CC FLAGS_REG))]
    "! TARGET_PARTIAL_REG_STALL && reload_completed
     && ((GET_MODE (operands[0]) == HImode
! 	&& ((!optimize_size && !TARGET_FAST_PREFIX)
              /* ??? next two lines just !satisfies_constraint_K (...) */
  	    || !CONST_INT_P (operands[2])
  	    || satisfies_constraint_K (operands[2])))
         || (GET_MODE (operands[0]) == QImode
! 	   && (TARGET_PROMOTE_QImode || optimize_size)))"
    [(parallel [(set (match_dup 0)
  		   (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
  	      (clobber (reg:CC FLAGS_REG))])]
--- 20340,20351 ----
     (clobber (reg:CC FLAGS_REG))]
    "! TARGET_PARTIAL_REG_STALL && reload_completed
     && ((GET_MODE (operands[0]) == HImode
! 	&& ((optimize_function_for_speed_p (cfun) && !TARGET_FAST_PREFIX)
              /* ??? next two lines just !satisfies_constraint_K (...) */
  	    || !CONST_INT_P (operands[2])
  	    || satisfies_constraint_K (operands[2])))
         || (GET_MODE (operands[0]) == QImode
! 	   && (TARGET_PROMOTE_QImode || optimize_function_for_size_p (cfun))))"
    [(parallel [(set (match_dup 0)
  		   (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
  	      (clobber (reg:CC FLAGS_REG))])]
***************
*** 20341,20347 ****
     (set (match_operand 1 "register_operand" "")
  	(and (match_dup 3) (match_dup 4)))]
    "! TARGET_PARTIAL_REG_STALL && reload_completed
!    && ! optimize_size
     && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
         || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))
     /* Ensure that the operand will remain sign-extended immediate.  */
--- 20368,20374 ----
     (set (match_operand 1 "register_operand" "")
  	(and (match_dup 3) (match_dup 4)))]
    "! TARGET_PARTIAL_REG_STALL && reload_completed
!    && optimize_insn_for_speed_p ()
     && ((GET_MODE (operands[1]) == HImode && ! TARGET_FAST_PREFIX)
         || (GET_MODE (operands[1]) == QImode && TARGET_PROMOTE_QImode))
     /* Ensure that the operand will remain sign-extended immediate.  */
Index: config/i386/sse.md
===================================================================
*** config/i386/sse.md	(revision 139728)
--- config/i386/sse.md	(working copy)
***************
*** 220,226 ****
  }
    [(set_attr "type" "sselog1,ssemov,ssemov")
     (set (attr "mode")
! 	(cond [(ior (ior (ne (symbol_ref "optimize_size") (const_int 0))
  			 (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
  		    (and (eq_attr "alternative" "2")
  			 (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
--- 220,226 ----
  }
    [(set_attr "type" "sselog1,ssemov,ssemov")
     (set (attr "mode")
! 	(cond [(ior (ior (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
  			 (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
  		    (and (eq_attr "alternative" "2")
  			 (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
***************
*** 656,662 ****
  		  (match_operand:V4SF 2 "nonimmediate_operand" "")))]
    "TARGET_SSE"
  {
!   if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
        && flag_finite_math_only && !flag_trapping_math
        && flag_unsafe_math_optimizations)
      {
--- 656,662 ----
  		  (match_operand:V4SF 2 "nonimmediate_operand" "")))]
    "TARGET_SSE"
  {
!   if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
        && flag_finite_math_only && !flag_trapping_math
        && flag_unsafe_math_optimizations)
      {
***************
*** 794,800 ****
  	(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
    "TARGET_SSE"
  {
!   if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_size
        && flag_finite_math_only && !flag_trapping_math
        && flag_unsafe_math_optimizations)
      {
--- 794,800 ----
  	(sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
    "TARGET_SSE"
  {
!   if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
        && flag_finite_math_only && !flag_trapping_math
        && flag_unsafe_math_optimizations)
      {
Index: config/i386/i386.c
===================================================================
*** config/i386/i386.c	(revision 139728)
--- config/i386/i386.c	(working copy)
*************** standard_80387_constant_p (rtx x)
*** 6843,6849 ****
    /* For XFmode constants, try to find a special 80387 instruction when
       optimizing for size or on those CPUs that benefit from them.  */
    if (mode == XFmode
!       && (optimize_size || TARGET_EXT_80387_CONSTANTS))
      {
        int i;
  
--- 6843,6849 ----
    /* For XFmode constants, try to find a special 80387 instruction when
       optimizing for size or on those CPUs that benefit from them.  */
    if (mode == XFmode
!       && (optimize_function_for_size_p (cfun) || TARGET_EXT_80387_CONSTANTS))
      {
        int i;
  
*************** ix86_compute_frame_layout (struct ix86_f
*** 7429,7435 ****
       Recompute the value as needed.  Do not recompute when amount of registers
       didn't change as reload does multiple calls to the function and does not
       expect the decision to change within single iteration.  */
!   if (!optimize_size
        && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
      {
        int count = frame->nregs;
--- 7429,7435 ----
       Recompute the value as needed.  Do not recompute when amount of registers
       didn't change as reload does multiple calls to the function and does not
       expect the decision to change within single iteration.  */
!   if (!optimize_function_for_size_p (cfun)
        && cfun->machine->use_fast_prologue_epilogue_nregs != frame->nregs)
      {
        int count = frame->nregs;
*************** ix86_expand_epilogue (int style)
*** 8176,8182 ****
  					    + frame.nregs * UNITS_PER_WORD),
  				   style);
        /* If not an i386, mov & pop is faster than "leave".  */
!       else if (TARGET_USE_LEAVE || optimize_size
  	       || !cfun->machine->use_fast_prologue_epilogue)
  	emit_insn ((*ix86_gen_leave) ());
        else
--- 8176,8182 ----
  					    + frame.nregs * UNITS_PER_WORD),
  				   style);
        /* If not an i386, mov & pop is faster than "leave".  */
!       else if (TARGET_USE_LEAVE || optimize_function_for_size_p (cfun)
  	       || !cfun->machine->use_fast_prologue_epilogue)
  	emit_insn ((*ix86_gen_leave) ());
        else
*************** ix86_decompose_address (rtx addr, struct
*** 8435,8442 ****
      disp = const0_rtx;
  
    /* Special case: on K6, [%esi] makes the instruction vector decoded.
!      Avoid this by transforming to [%esi+0].  */
!   if (TARGET_K6 && !optimize_size
        && base_reg && !index_reg && !disp
        && REG_P (base_reg)
        && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
--- 8435,8444 ----
      disp = const0_rtx;
  
    /* Special case: on K6, [%esi] makes the instruction vector decoded.
!      Avoid this by transforming to [%esi+0].
!      Reload calls address legitimization without cfun defined, so we need
!      to test cfun for being non-NULL. */
!   if (TARGET_K6 && cfun && optimize_function_for_speed_p (cfun)
        && base_reg && !index_reg && !disp
        && REG_P (base_reg)
        && REGNO_REG_CLASS (REGNO (base_reg)) == SIREG)
*************** print_operand (FILE *file, rtx x, int co
*** 10736,10742 ****
  	  {
  	    rtx x;
  
! 	    if (!optimize || optimize_size || !TARGET_BRANCH_PREDICTION_HINTS)
  	      return;
  
  	    x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
--- 10738,10745 ----
  	  {
  	    rtx x;
  
! 	    if (!optimize
! 	        || optimize_function_for_size_p (cfun) || !TARGET_BRANCH_PREDICTION_HINTS)
  	      return;
  
  	    x = find_reg_note (current_output_insn, REG_BR_PROB, 0);
*************** emit_i387_cw_initialization (int mode)
*** 11503,11509 ****
    emit_insn (gen_x86_fnstcw_1 (stored_mode));
    emit_move_insn (reg, copy_rtx (stored_mode));
  
!   if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL || optimize_size)
      {
        switch (mode)
  	{
--- 11506,11513 ----
    emit_insn (gen_x86_fnstcw_1 (stored_mode));
    emit_move_insn (reg, copy_rtx (stored_mode));
  
!   if (TARGET_64BIT || TARGET_PARTIAL_REG_STALL
!       || optimize_function_for_size_p (cfun))
      {
        switch (mode)
  	{
*************** inline_memory_move_cost (enum machine_mo
*** 24914,24920 ****
  	  {
  	    if (!in)
  	      return ix86_cost->int_store[0];
! 	    if (TARGET_PARTIAL_REG_DEPENDENCY && !optimize_size)
  	      cost = ix86_cost->movzbl_load;
  	    else
  	      cost = ix86_cost->int_load[0];
--- 24918,24925 ----
  	  {
  	    if (!in)
  	      return ix86_cost->int_store[0];
! 	    if (TARGET_PARTIAL_REG_DEPENDENCY
! 	        && optimize_function_for_speed_p (cfun))
  	      cost = ix86_cost->movzbl_load;
  	    else
  	      cost = ix86_cost->int_load[0];
*************** ix86_pad_returns (void)
*** 26150,26158 ****
  static void
  ix86_reorg (void)
  {
!   if (TARGET_PAD_RETURNS && optimize && !optimize_size)
      ix86_pad_returns ();
!   if (TARGET_FOUR_JUMP_LIMIT && optimize && !optimize_size)
      ix86_avoid_jump_misspredicts ();
  }
  
--- 26155,26165 ----
  static void
  ix86_reorg (void)
  {
!   if (TARGET_PAD_RETURNS && optimize
!       && optimize_function_for_speed_p (cfun))
      ix86_pad_returns ();
!   if (TARGET_FOUR_JUMP_LIMIT && optimize
!       && optimize_function_for_speed_p (cfun))
      ix86_avoid_jump_misspredicts ();
  }
  


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