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Re: PATCH: PR target/35189: -mno-sse4.2 turns off SSE4a
Hi,
My last patch doesn't work for "-msse5 -mno-sse[23]". For -mA, if A
implies B, -mA
enables -mB and -mno-B disables -mA. At the beginning. none of SSEs is enabled.
When ix86_handle_option sees -msse5, it turns on only SSE5. When
override_options is
called, if SSE5 is turned on, it turns on SSE4A which turns on SSE3
which turns on SSE2
which turns on SSE. When ix86_handle_option sees -mno-sse2, it turns
off SSE3, SSE4,
SSE4A, SSE5.
For "-msse5 -mno-sse2", when override_options is called after
ix86_handle_option,
SSE5 is turned off, As the result, none of SSEs is turned on.
This patch changes ix86_handle_option to turn on all implied SSE/MMX features
and changes override_options not to turn on any implied SSE/MMX features while
only turning on MMX if SSE is enabled.
H.J.
On Feb 17, 2008 7:35 AM, H.J. Lu <hjl.tools@gmail.com> wrote:
>
> On Thu, Feb 14, 2008 at 07:56:11AM +0100, Uros Bizjak wrote:
> > Hello!
> >
> > > > SSE4A is independent of SSSE3 and SSE4. Turn off one shouldn't
> > > > turn off the other. Also I think that SSE5 implies SSE4A. Does this
> > > > patch make senses. If yes,. I can add a few testcases.
> > > >
> > >
> > > Here is the patch with testcases. OK for 4.3?
> >
> > This patch can be committed to 4.3 as obvious, after Michael confirms
> > that it is OK for AMD targets.
> >
>
> It turned out that I missed OPTION_MASK_ISA_SSE4A_UNSET.
> "-msse5 -mno-sse[23]" won't work correctly. Here is an updated
> patch with new testcases.
>
>
gcc/
2008-02-17 H.J. Lu <hongjiu.lu@intel.com>
PR target/35189
* config/i386/i386.c (OPTION_MASK_ISA_MMX_SET): New.
(OPTION_MASK_ISA_3DNOW_SET): Likewise.
(OPTION_MASK_ISA_SSE_SET): Likewise.
(OPTION_MASK_ISA_SSE2_SET): Likewise.
(OPTION_MASK_ISA_SSE3_SET): Likewise.
(OPTION_MASK_ISA_SSSE3_SET): Likewise.
(OPTION_MASK_ISA_SSE4_1_SET): Likewise.
(OPTION_MASK_ISA_SSE4_2_SET): Likewise.
(OPTION_MASK_ISA_SSE4_SET): Likewise.
(OPTION_MASK_ISA_SSE4A_SET): Likewise.
(OPTION_MASK_ISA_SSE5_SET): Likewise.
(OPTION_MASK_ISA_SSE3_UNSET): Add
OPTION_MASK_ISA_SSE4A and OPTION_MASK_ISA_SSE4A_UNSET.
(OPTION_MASK_ISA_SSE4_2_UNSET): Set to 0.
(OPTION_MASK_ISA_SSE4A_UNSET): Set to OPTION_MASK_ISA_SSE5.
(ix86_handle_option): Turn on bits in ix86_isa_flags with
OPTION_MASK_ISA_XXX_SET.
(override_options): Don't turn on implied SSE/MMX bits in
ix86_isa_flags.
gcc/testsuite/
2008-02-17 H.J. Lu <hongjiu.lu@intel.com>
PR target/35189
* gcc.target/i386/isa-1.c: New.
* gcc.target/i386/isa-2.c: Likewise.
* gcc.target/i386/isa-3.c: Likewise.
* gcc.target/i386/isa-4.c: Likewise.
* gcc.target/i386/isa-5.c: Likewise.
* gcc.target/i386/isa-6.c: Likewise.
* gcc.target/i386/isa-7.c: Likewise.
* gcc.target/i386/isa-8.c: Likewise.
* gcc.target/i386/isa-9.c: Likewise.
* gcc.target/i386/isa-10.c: Likewise.
* gcc.target/i386/isa-11.c: Likewise.
* gcc.target/i386/isa-12.c: Likewise.
* gcc.target/i386/isa-13.c: Likewise.
* gcc.target/i386/isa-14.c: Likewise.
--- gcc/config/i386/i386.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/config/i386/i386.c 2008-02-17 11:10:24.000000000 -0800
@@ -1768,6 +1768,34 @@ int ix86_isa_flags = TARGET_64BIT_DEFAUL
was set or cleared on the command line. */
static int ix86_isa_flags_explicit;
+/* Define a set of ISAs which are available for a given ISA. MMX
+ and SSE ISAs are handled separately. */
+
+#define OPTION_MASK_ISA_MMX_SET OPTION_MASK_ISA_MMX
+#define OPTION_MASK_ISA_3DNOW_SET \
+ (OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_MMX_SET)
+
+#define OPTION_MASK_ISA_SSE_SET OPTION_MASK_ISA_SSE
+#define OPTION_MASK_ISA_SSE2_SET \
+ (OPTION_MASK_ISA_SSE2 | OPTION_MASK_ISA_SSE_SET)
+#define OPTION_MASK_ISA_SSE3_SET \
+ (OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE2_SET)
+#define OPTION_MASK_ISA_SSSE3_SET \
+ (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSE3_SET)
+#define OPTION_MASK_ISA_SSE4_1_SET \
+ (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSSE3_SET)
+#define OPTION_MASK_ISA_SSE4_2_SET \
+ (OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_1_SET)
+
+/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
+ as -msse4.1 -msse4.2. */
+#define OPTION_MASK_ISA_SSE4_SET OPTION_MASK_ISA_SSE4_2_SET
+
+#define OPTION_MASK_ISA_SSE4A_SET \
+ (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
+#define OPTION_MASK_ISA_SSE5_SET \
+ (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
+
/* Define a set of ISAs which aren't available for a given ISA. MMX
and SSE ISAs are handled separately. */
@@ -1780,12 +1808,15 @@ static int ix86_isa_flags_explicit;
#define OPTION_MASK_ISA_SSE2_UNSET \
(OPTION_MASK_ISA_SSE3 | OPTION_MASK_ISA_SSE3_UNSET)
#define OPTION_MASK_ISA_SSE3_UNSET \
- (OPTION_MASK_ISA_SSSE3 | OPTION_MASK_ISA_SSSE3_UNSET)
+ (OPTION_MASK_ISA_SSSE3 \
+ | OPTION_MASK_ISA_SSSE3_UNSET \
+ | OPTION_MASK_ISA_SSE4A \
+ | OPTION_MASK_ISA_SSE4A_UNSET )
#define OPTION_MASK_ISA_SSSE3_UNSET \
(OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_1_UNSET)
#define OPTION_MASK_ISA_SSE4_1_UNSET \
(OPTION_MASK_ISA_SSE4_2 | OPTION_MASK_ISA_SSE4_2_UNSET)
-#define OPTION_MASK_ISA_SSE4_2_UNSET OPTION_MASK_ISA_SSE4A
+#define OPTION_MASK_ISA_SSE4_2_UNSET 0
/* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same
as -msse4.1 -msse4.2. -mno-sse4 should the same as -mno-sse4.1. */
@@ -1793,7 +1824,7 @@ static int ix86_isa_flags_explicit;
(OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE4_2)
#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
-#define OPTION_MASK_ISA_SSE4A_UNSET OPTION_MASK_ISA_SSE4
+#define OPTION_MASK_ISA_SSE4A_UNSET OPTION_MASK_ISA_SSE5
#define OPTION_MASK_ISA_SSE5_UNSET \
(OPTION_MASK_ISA_3DNOW | OPTION_MASK_ISA_3DNOW_UNSET)
@@ -1816,6 +1847,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_MMX_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_MMX_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_MMX_SET;
return true;
case OPT_m3dnow:
@@ -1825,6 +1858,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_3DNOW_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_3DNOW_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_3DNOW_SET;
return true;
case OPT_m3dnowa:
@@ -1837,6 +1872,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_SSE_SET;
return true;
case OPT_msse2:
@@ -1846,6 +1883,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE2_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE2_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_SSE2_SET;
return true;
case OPT_msse3:
@@ -1855,6 +1894,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE3_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE3_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_SSE3_SET;
return true;
case OPT_mssse3:
@@ -1864,6 +1905,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_SSSE3_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSSE3_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_SSSE3_SET;
return true;
case OPT_msse4_1:
@@ -1873,6 +1916,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_1_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_1_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1_SET;
return true;
case OPT_msse4_2:
@@ -1882,11 +1927,13 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4_2_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_2_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_SSE4_2_SET;
return true;
case OPT_msse4:
- ix86_isa_flags |= OPTION_MASK_ISA_SSE4;
- ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4;
+ ix86_isa_flags |= OPTION_MASK_ISA_SSE4_SET;
+ ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4_SET;
return true;
case OPT_mno_sse4:
@@ -1901,6 +1948,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE4A_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE4A_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_SSE4A_SET;
return true;
case OPT_msse5:
@@ -1910,6 +1959,8 @@ ix86_handle_option (size_t code, const c
ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
}
+ else
+ ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
return true;
default:
@@ -2532,34 +2583,6 @@ override_options (void)
if (!TARGET_80387)
target_flags |= MASK_NO_FANCY_MATH_387;
- /* Turn on SSE4A bultins for -msse5. */
- if (TARGET_SSE5)
- ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
-
- /* Turn on SSE4.1 builtins for -msse4.2. */
- if (TARGET_SSE4_2)
- ix86_isa_flags |= OPTION_MASK_ISA_SSE4_1;
-
- /* Turn on SSSE3 builtins for -msse4.1. */
- if (TARGET_SSE4_1)
- ix86_isa_flags |= OPTION_MASK_ISA_SSSE3;
-
- /* Turn on SSE3 builtins for -mssse3. */
- if (TARGET_SSSE3)
- ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
-
- /* Turn on SSE3 builtins for -msse4a. */
- if (TARGET_SSE4A)
- ix86_isa_flags |= OPTION_MASK_ISA_SSE3;
-
- /* Turn on SSE2 builtins for -msse3. */
- if (TARGET_SSE3)
- ix86_isa_flags |= OPTION_MASK_ISA_SSE2;
-
- /* Turn on SSE builtins for -msse2. */
- if (TARGET_SSE2)
- ix86_isa_flags |= OPTION_MASK_ISA_SSE;
-
/* Turn on MMX builtins for -msse. */
if (TARGET_SSE)
{
@@ -2567,10 +2590,6 @@ override_options (void)
x86_prefetch_sse = true;
}
- /* Turn on MMX builtins for 3Dnow. */
- if (TARGET_3DNOW)
- ix86_isa_flags |= OPTION_MASK_ISA_MMX;
-
/* Turn on popcnt instruction for -msse4.2 or -mabm. */
if (TARGET_SSE4_2 || TARGET_ABM)
x86_popcnt = true;
--- gcc/testsuite/gcc.target/i386/isa-1.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-1.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if !defined __SSSE3__
+ abort ();
+#endif
+#if !defined __SSE4_1__
+ abort ();
+#endif
+#if !defined __SSE4_2__
+ abort ();
+#endif
+#if defined __SSE4A__
+ abort ();
+#endif
+#if defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-10.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-10.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse5 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if !defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-11.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-11.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse5 -mno-ssse3" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if !defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-12.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-12.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse5 -mno-sse3" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if defined __SSE4A__
+ abort ();
+#endif
+#if defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-13.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-13.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse5 -mno-sse2" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if defined __SSE2__
+ abort ();
+#endif
+#if defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if defined __SSE4A__
+ abort ();
+#endif
+#if defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-14.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-14.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse5 -mno-sse" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if defined __SSE__
+ abort ();
+#endif
+#if defined __SSE2__
+ abort ();
+#endif
+#if defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if defined __SSE4A__
+ abort ();
+#endif
+#if defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-2.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-2.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse4 -msse5" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if !defined __SSSE3__
+ abort ();
+#endif
+#if !defined __SSE4_1__
+ abort ();
+#endif
+#if !defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if !defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-3.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-3.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-msse4 -msse5 -msse4a" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if !defined __SSSE3__
+ abort ();
+#endif
+#if !defined __SSE4_1__
+ abort ();
+#endif
+#if !defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if !defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-4.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-4.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=core2 -msse5 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if !defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if !defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-5.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-5.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=core2 -msse4a -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if !defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-6.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-6.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-7.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-7.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -msse5 -mno-sse4" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if !defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-8.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-8.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -msse5 -mno-sse4a" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if defined __SSE4A__
+ abort ();
+#endif
+#if defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}
--- gcc/testsuite/gcc.target/i386/isa-9.c.sse4a 2008-02-17 07:29:24.000000000 -0800
+++ gcc/testsuite/gcc.target/i386/isa-9.c 2008-02-17 07:29:24.000000000 -0800
@@ -0,0 +1,34 @@
+/* { dg-do run } */
+/* { dg-options "-march=amdfam10 -mno-sse5" } */
+
+extern void abort (void);
+
+int
+main ()
+{
+#if !defined __SSE__
+ abort ();
+#endif
+#if !defined __SSE2__
+ abort ();
+#endif
+#if !defined __SSE3__
+ abort ();
+#endif
+#if defined __SSSE3__
+ abort ();
+#endif
+#if defined __SSE4_1__
+ abort ();
+#endif
+#if defined __SSE4_2__
+ abort ();
+#endif
+#if !defined __SSE4A__
+ abort ();
+#endif
+#if defined __SSE5__
+ abort ();
+#endif
+ return 0;
+}