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Re: [PATCH][i386] Fix PR 6585 redundant movl instructions

Hello Rask!

In PR 6585 we have a case of poor register allocation because of the
DImode destination in a widening multiply:


   It records a conflict between register 61 and 66 and ends up allocating
register 61 to (%esi:%ebx) where we would prefer (%edx:%eax). This patch
fixes it by splitting the DImode destination into two SImode parts before
register allocation, which allows the second subreg lowering pass to replace
the subregs with plain SImode regs which the register allocator can handle.
The result is much better:

	pushl	%ebx			# 40	*pushsi2	[length = 1]
	movl	8(%esp), %ebx		# 28	*movsi_1/1	[length = 4]
	movl	16(%esp), %eax		# 30	*movsi_1/1	[length = 4]
	movl	20(%esp), %ecx		# 37	*movsi_1/1	[length = 4]
	movl	12(%esp), %edx		# 38	*movsi_1/1	[length = 4]
	imull	%ebx, %ecx		# 7	*mulsi3_1/3	[length = 3]
	imull	%eax, %edx		# 8	*mulsi3_1/3	[length = 3]
	addl	%edx, %ecx		# 9	*addsi_1/1	[length = 2]
	mull	%ebx			# 33	*umulsidi3	[length = 2]
	popl	%ebx			# 43	popsi1	[length = 1]
	leal	(%ecx,%edx), %edx	# 39	*lea_1	[length = 3]
	ret				# 44	return_internal	[length = 1]

I'm afraid that your patch is just papering over a real problem with register allocator (as you described above). However, current *umulsidi3_insn correctly describes widening mul insn, and as shown in PR 17236, RA can be fixed to solve this problem in a generic way. The later patch also handles possible problems with *umulditi3 on 64bit targets.

The only problem that remains is, that for recent x86 targets, it is cheaper to propagate 8(%esp) into two (or more?) places than to use %ebx register. it looks that this functionality is missing from gcc.


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