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Re: [PATCH] Create VECTOR_CST instead of CONSTRUCTORs where possible in the vectorizer (PR tree-optimization/33993)


On Tue, Nov 06, 2007 at 07:21:51PM -0800, Dorit Nuzman wrote:
> These appeared on powerpc64-linux since the commit of this patch (r129920):
> 
> FAIL: gcc.dg/vect/no-scevccp-outer-10a.c execution test
> FAIL: gcc.dg/vect/no-scevccp-outer-10b.c execution test
> FAIL: gcc.dg/vect/no-scevccp-outer-11.c execution test
> FAIL: gcc.dg/vect/no-scevccp-outer-12.c execution test
> FAIL: gcc.dg/vect/no-scevccp-outer-15.c execution test
> FAIL: gcc.dg/vect/no-scevccp-outer-22.c execution test
> FAIL: gcc.dg/vect/no-scevccp-outer-7.c execution test
> FAIL: gcc.dg/vect/no-scevccp-noreassoc-outer-3.c execution test

Yeah, I can reproduce that, but it just seems to uncover a latent bug rather
than be a bug in the patch.  In fact, if there wasn't this latent bug, with
the patch we generate far more efficient code, which is why I wonder if
the expander shouldn't check for VECTOR_TYPE CONSTRUCTORs with all entries
CONSTANT_CLASS_P and turn them into (or just expand them as) a VECTOR_CST.

>From what I can see, gcc.dg/vect/no-scevccp-outer-10a.c is miscompiled
during sched2, where the scheduler happily moves set of v1 (and v12)
register accross a function call, in the former case it is not fatal on
Altivec CPUs (the vspltisw 1,4 insn is just moved before bl check_vector,
which means e.g. that on non-Altivec CPUs this will SIGILL), but in the
latter (vspltisw 12,4 insn moved in front of bl foo where it is used after
it) is fatal.  Because:
  if (TARGET_ALTIVEC_ABI)
    {
      for (i = FIRST_ALTIVEC_REGNO; i < FIRST_ALTIVEC_REGNO + 20; ++i)
        call_used_regs[i] = call_really_used_regs[i] = 1;
and so both v1 and v12 are call used.

	Jakub


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