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Re: Debugging line numbers for delayed branches


Daniel Jacobowitz wrote:
I have been working on GDB support for optimized code.  This turns up
all sorts of interesting quirks in GCC's debug output when optimizing.

I recall that I had a problem when NOT optimising - I was getting line numbers starting in delay slots even at -O0 (when the slot contained nothing but a 'nop'). This was on an SH-4 target.


This is a particularly evil problem on SH where one cannot place breakpoints in delay slots. It's made worse because there is no general way to determine if an instruction is in a delay slot, or not, by instruction analysis alone.

Unfortunately I do not have any example code to hand.

Andrew


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