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Re: New back end ia16: 16-bit Intel x86
- From: Daniel Jacobowitz <drow at false dot org>
- To: Rask Ingemann Lambertsen <rask at sygehus dot dk>
- Cc: Uros Bizjak <ubizjak at gmail dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>, Jan Hubicka <jh at suse dot cz>, Richard Kenner <kenner at vlsi1 dot ultra dot nyu dot edu>, rridge at csclub dot uwaterloo dot ca
- Date: Tue, 7 Aug 2007 13:37:09 -0400
- Subject: Re: New back end ia16: 16-bit Intel x86
- References: <46B72E64.6070007@gmail.com> <20070807012933.GW25795@sygehus.dk>
On Tue, Aug 07, 2007 at 03:29:33AM +0200, Rask Ingemann Lambertsen wrote:
> > As an example, existing MIPS backend covers all targets from one code
> > base, ranging from embedded 16bit to 64bit targets.
>
> I'm no MIPS expert, but isn't MIPS16 mainly a compact instruction
> encoding, with a reduction in the available instructions and two-operand
> instructions to make the encoding fit into 16 bits?
That's correct.
--
Daniel Jacobowitz
CodeSourcery