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Fix ARM build (PR32753)
- From: Paul Brook <paul at codesourcery dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 16 Jul 2007 14:00:58 +0100
- Subject: Fix ARM build (PR32753)
arm/cirrus.md contains a disabled pattern for SImode values in cirrus regs.
Under most circumstances genconditions eliminates the pattern before the rest
of gen* notice how bogus it is. However genconditions requires at least
gcc3.0.1 to operate fully, so the build fails with old 2.95 host compilers.
The pattern is sufficiently bitrotten that I don't see any value in keeping
it. The attached patch removes it, leaving the comment mentioning that the
omission is deliberate.
Paul
2007-07-16 Paul Brook <paul@codesourcery.com>
PR target/32753
gcc/
* config/arm/cirrus.md (cirrus_arm_movsi_insn): Remove dead insn.
Index: gcc/config/arm/cirrus.md
===================================================================
--- gcc/config/arm/cirrus.md (revision 126588)
+++ gcc/config/arm/cirrus.md (working copy)
@@ -404,28 +404,6 @@ (define_insn "*cirrus_arm_movdi"
;; Cirrus SI values have been outlawed. Look in arm.h for the comment
;; on HARD_REGNO_MODE_OK.
-(define_insn "*cirrus_arm_movsi_insn"
- [(set (match_operand:SI 0 "general_operand" "=r,r,r,m,*v,r,*v,T,*v")
- (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,*v,T,*v,*v"))]
- "TARGET_ARM && TARGET_HARD_FLOAT && TARGET_MAVERICK && 0
- && (register_operand (operands[0], SImode)
- || register_operand (operands[1], SImode))"
- "@
- mov%?\\t%0, %1
- mvn%?\\t%0, #%B1
- ldr%?\\t%0, %1
- str%?\\t%1, %0
- cfmv64lr%?\\t%Z0, %1
- cfmvr64l%?\\t%0, %Z1
- cfldr32%?\\t%V0, %1
- cfstr32%?\\t%V1, %0
- cfsh32%?\\t%V0, %V1, #0"
- [(set_attr "type" "*, *, load1,store1, *, *, load1,store1, *")
- (set_attr "pool_range" "*, *, 4096, *, *, *, 1024, *, *")
- (set_attr "neg_pool_range" "*, *, 4084, *, *, *, 1012, *, *")
- (set_attr "cirrus" "not,not, not, not,move,normal,normal,normal,normal")]
-)
-
(define_insn "*cirrus_movsf_hard_insn"
[(set (match_operand:SF 0 "nonimmediate_operand" "=v,v,v,r,m,r,r,m")
(match_operand:SF 1 "general_operand" "v,mE,r,v,v,r,mE,r"))]