Re: [PING][PATCH][REVISED] Fix PR middle-end/PR28690, modify swap_commutative_operands_p

[Peter Bergner <bergner at vnet dot ibm dot com>]

On Sat, 2007-07-14 at 09:56 -0700, H.J. Lu wrote:
> So the order Power 6 prefers is
>
> 1. REG_POINTER
> 2. MEM_POINTER
> 3. REG_P
> 4. MEM_P

That is how the code has it now, although 4. is really everything that
isn't a REG_POINTER, MEM_POINTER or REG_P.  Originally, I had the code
setup for:
  1. REG_POINTER
  2. REG
  3. Everything else.
However, I hit a few test cases were we were passed a MEM_POINTER and
a REG which would cause the REG to be put before the MEM_POINTER.
Now the POWER ISA only has REG+CONST and REG+REG addressing modes, so
the MEM_POINTER was eventually forced into a register, but by then, we'd
already made the decision that it was the second operand which isn't
the way we want it.  That's why MEM_POINTER's are now sorted before
REGs.

 
> Will
> 
> 1. REG_POINTER
> 2. MEM_POINTER
> 3. REG_P/MEM_P
> 
> work for you. 
> 
> Also will
> 
> 1. REG_POINTER/MEM_POINTER
> 2. REG_P/MEM_P
> 
> work for you.

Without having actually tried it, I'm guessing they would work from the
standpoint that we probably would get the order of the indexed load or
store operands in the correct order.  However, by mixing REGs and MEMs,
we'll possibly reduce the chances of some canonicalizations.  An example
would be: r1 + *p - r1.  Although, those aren't being caught now with
current mainline either.

Did you try removing the REGno sorting from swap_commutative_operands_p
and see if that helps like I suggested?  Did you try Paolo's suggestion
of using -frename-registers?

Peter