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Re: ARM: enable interpreter, add locks code
- From: Daniel Jacobowitz <drow at false dot org>
- To: David Daney <ddaney at avtrex dot com>
- Cc: Andrew Haley <aph-gcc at littlepinkcloud dot COM>, java-patches at gcc dot gnu dot org, gcc-patches at gcc dot gnu dot org
- Date: Wed, 11 Jul 2007 17:47:57 -0400
- Subject: Re: ARM: enable interpreter, add locks code
- References: <firstname.lastname@example.org> <email@example.com>
On Wed, Jul 11, 2007 at 12:58:28PM -0700, David Daney wrote:
> Andrew Haley wrote:
> > +/* Atomic compare and exchange. These sequences are not actually
> > + atomic; there is a race if *ADDR != OLD_VAL and we are preempted
> > + between the two swaps. However, they are very close to atomic, and
> > + are the best that a pre-ARMv6 implementation can do without
> > + operating system support. LinuxThreads has been using these
> > + sequences for many years. */
> Wow! That is terrible.
Actually it works very well :-)
> Is there some way to do proper synchronization if the target CPU supports it?
You would have to configure gcc specifically for an armv6 or armv7
processor, or add relevant multilibs. Or require a sufficiently
recent kernel, which has magic for this. There's no ready way to
check at runtime without a performance hit.