Re: [PATCH, rtl]: Change VEC_* expressions to RTX_EXTRA class.

[Uros Bizjak <ubizjak at gmail dot com>]

Rob1weld@aol.com wrote:

> > It is common for many programs (that check cpu type) to think I have a  
> > Opteron (K8) when actually it _might_ be a K7 (technically)
> >  
> >
> > fpu              : yes
> > flags           : fpu  vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca 
> > cmov pat pse36 clfl mmx  fxsr sse syscall mmxext lm 3dnowext  3dnow
> >     

According to cpu flags your processor doesn't support SSE2.

> > I can compile GCC using the environment variable "CC=gcc -mfpmath=sse,387"  
> > and double the number of fp registers. This works (in the past)
> >     

The performance of -mfpmath=sse,387 depends on the target. If your FP 
code is mostly operating on "double" types, SSE1 target won't make 
difference, as all "double" values are already in x87 registers. But for 
SSE2 target, register allocator can't make a clear choice, what to put 
in XMM registers and what to x87 registers. Code using -mfpmath=sse,387 
works faster because it enables all (fast) x87 instructions, like fsin, 
log, fsincos, etc... for -ffast-math option, but requires (slow) moves 
between XMM and x87 register sets. We are still waiting for the 
resolution on libgccmath that would fix this problem for pure SSE code.

> > I can also use the -mssse3 -msse4.1 instructions with my processor but  
> > (unfortunately) the tests have been made "unsupported" in many instances
> > to avoid getting the correct tests to run on the correct processor under  all 
> > circumstances - without a flood of error reports.
> >     

"unsupported" in this context means that your toolchain can't generate 
object code with certain instructions. When new binutils will be 
released, these instructions will be supported, but your processor won't 
be able to execute this binary. The tests have a special "pass" path in 
case your processor doesn't support this insn, still reporting success.

Uros.