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Re: PATCH: Add SSE4.2 support
On Wed, May 23, 2007 at 01:02:22PM -0700, Mike Stump wrote:
> On May 23, 2007, at 7:32 AM, Uros Bizjak wrote:
> >For clarity, all uses of TARGET_SSExxx should be turned into
> >OPTION_SSExxx. Does somebody already have a script that would
> >process all sources in the directory and make this change?
>
> You can #define TARGET_SSExxx OPTION_SSExxx
>
> Cheap, maybe.... I was toying with things like this for rs6000 due
> to running out of bits, and I didn't like the name change either...
>
> but, if you want, you can use emacs's tags-query-replace...
Here is my approach. I don't think OPTION_MASK_XXX is very useful
since you can always use Mask(FOO_XXX) to get MASK_FOO_XXX. As for
OPTION_XXX, it is no better than TARGET_XXX. We may have more
than one set of OPTION_XXXs. TARGET_FOO_XXX is more consistent than
OPTION_XXX. Many target mask flags need an explicit flag, like
int target_flags_explicit;
There is no need to specialized target_flags. We can always add a
int xxxx_explicit;
for
int xxxx;
if xxxx is a target mask flag.
H.J.
----
2007-05-23 H.J. Lu <hongjiu.lu@intel.com>
* config.gcc (i[34567]86-*-*): Add i386/isa.opt to
extra_options.
(x86_64-*-*): Likewise.
* config/i386/darwin.h (TARGET_64BIT): Replace target_flags
with target_isa_flags.
* config/i386/i386.c (ix86_handle_option): Replace target_flags
and target_flags_explicit with target_isa_flags and
target_isa_flags_explicit, respectively, for ISA masks.
(override_options): Likewise.
(override_options): Add target_isa_enable and target_isa_disable
fields to processor_costs. Adjust processor_target_table.
(def_builtin): Replace target_flags with target_isa_flags.
(TARGET_DEFAULT_TARGET_FLAGS): Remove TARGET_64BIT_DEFAULT.
* config/i386/i386.h (TARGET_ISA_SUBTARGET64_DEFAULT): New.
* config/i386/i386.opt (m64): Moved to config/i386/isa.opt.
(m32): Likewise.
(m3dnow): Likewise.
(mmmx): Likewise.
(msse): Likewise.
(msse2): Likewise.
(msse3): Likewise.
(mssse3): Likewise.
(msse4.1): Likewise.
(msse4a): Likewise.
(3DNOW_A): Likewise.
* config/i386/isa.opt: New file.
* config/linux.h (TARGET_C99_FUNCTIONS): Replace OPTION_GLIBC
with TARGET_GLIBC.
(TARGET_HAS_SINCOS): Likewise.
* config/linux.opt (muclibc): Likewise.
* opt-functions.awk (var_set): Use MASK_ for target mask flag.
(flag_target_mask_p): New.
(var_ref): Add _explicit variable reference for target mask
flag.
* optc-gen.awk: Use MASK_ and TARGET_ for target mask flag.
Treate target_flags as the default target mask flag.
* opth-gen.awk: Likewise.
* opts.h (cl_option): Add flag_explicit_var.
* opts.c (handle_option): Don't check target_flags_explicit.
Update flag_explicit_var if it isn't NULL.
* rtlanal.c (target_flags): Removed.
* toplev.c (target_flags): Likewise.
(target_flags_explicit): Removed.
* toplev.h (target_flags_explicit): Likewise.
--- gcc/config.gcc.isa 2007-05-22 10:58:08.000000000 -0700
+++ gcc/config.gcc 2007-05-23 10:33:25.000000000 -0700
@@ -277,11 +277,13 @@ i[34567]86-*-*)
cpu_type=i386
extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h
pmmintrin.h tmmintrin.h ammintrin.h smmintrin.h"
+ extra_options="${extra_options} i386/isa.opt"
;;
x86_64-*-*)
cpu_type=i386
extra_headers="mmintrin.h mm3dnow.h xmmintrin.h emmintrin.h
pmmintrin.h tmmintrin.h ammintrin.h smmintrin.h"
+ extra_options="${extra_options} i386/isa.opt"
need_64bit_hwint=yes
;;
ia64-*-*)
--- gcc/config/i386/darwin.h.isa 2007-03-27 09:25:33.000000000 -0700
+++ gcc/config/i386/darwin.h 2007-05-23 14:04:35.000000000 -0700
@@ -26,7 +26,7 @@ Boston, MA 02110-1301, USA. */
#define TARGET_VERSION fprintf (stderr, " (i686 Darwin)");
#undef TARGET_64BIT
-#define TARGET_64BIT (target_flags & MASK_64BIT)
+#define TARGET_64BIT (target_isa_flags & MASK_64BIT)
#ifdef IN_LIBGCC2
#undef TARGET_64BIT
--- gcc/config/i386/i386.c.isa 2007-05-23 10:31:47.000000000 -0700
+++ gcc/config/i386/i386.c 2007-05-23 16:23:54.000000000 -0700
@@ -1554,69 +1554,70 @@ ix86_handle_option (size_t code, const c
case OPT_m3dnow:
if (!value)
{
- target_flags &= ~MASK_3DNOW_A;
- target_flags_explicit |= MASK_3DNOW_A;
+ target_isa_flags &= ~MASK_3DNOW_A;
+ target_isa_flags_explicit |= MASK_3DNOW_A;
}
return true;
case OPT_mmmx:
if (!value)
{
- target_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
- target_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
+ target_isa_flags &= ~(MASK_3DNOW | MASK_3DNOW_A);
+ target_isa_flags_explicit |= MASK_3DNOW | MASK_3DNOW_A;
}
return true;
case OPT_msse:
if (!value)
{
- target_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
- | MASK_SSE4_1 | MASK_SSE4A);
- target_flags_explicit |= (MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
- | MASK_SSE4_1 | MASK_SSE4A);
+ target_isa_flags &= ~(MASK_SSE2 | MASK_SSE3 | MASK_SSSE3
+ | MASK_SSE4_1 | MASK_SSE4A);
+ target_isa_flags_explicit |= (MASK_SSE2 | MASK_SSE3
+ | MASK_SSSE3 | MASK_SSE4_1
+ | MASK_SSE4A);
}
return true;
case OPT_msse2:
if (!value)
{
- target_flags &= ~(MASK_SSE3 | MASK_SSSE3 | MASK_SSE4_1
- | MASK_SSE4A);
- target_flags_explicit |= (MASK_SSE3 | MASK_SSSE3
- | MASK_SSE4_1 | MASK_SSE4A);
+ target_isa_flags &= ~(MASK_SSE3 | MASK_SSSE3 | MASK_SSE4_1
+ | MASK_SSE4A);
+ target_isa_flags_explicit |= (MASK_SSE3 | MASK_SSSE3
+ | MASK_SSE4_1 | MASK_SSE4A);
}
return true;
case OPT_msse3:
if (!value)
{
- target_flags &= ~(MASK_SSSE3 | MASK_SSE4_1 | MASK_SSE4A);
- target_flags_explicit |= (MASK_SSSE3 | MASK_SSE4_1
- | MASK_SSE4A);
+ target_isa_flags &= ~(MASK_SSSE3 | MASK_SSE4_1 | MASK_SSE4A);
+ target_isa_flags_explicit |= (MASK_SSSE3 | MASK_SSE4_1
+ | MASK_SSE4A);
}
return true;
case OPT_mssse3:
if (!value)
{
- target_flags &= ~(MASK_SSE4_1 | MASK_SSE4A);
- target_flags_explicit |= MASK_SSE4_1 | MASK_SSE4A;
+ target_isa_flags &= ~(MASK_SSE4_1 | MASK_SSE4A);
+ target_isa_flags_explicit |= MASK_SSE4_1 | MASK_SSE4A;
}
return true;
case OPT_msse4_1:
if (!value)
{
- target_flags &= ~MASK_SSE4A;
- target_flags_explicit |= MASK_SSE4A;
+ target_isa_flags &= ~MASK_SSE4A;
+ target_isa_flags_explicit |= MASK_SSE4A;
}
return true;
case OPT_msse4a:
if (!value)
{
- target_flags &= ~MASK_SSE4_1;
- target_flags_explicit |= MASK_SSE4_1;
+ target_isa_flags &= ~MASK_SSE4_1;
+ target_isa_flags_explicit |= MASK_SSE4_1;
}
return true;
@@ -1649,6 +1650,8 @@ override_options (void)
const struct processor_costs *cost; /* Processor costs */
const int target_enable; /* Target flags to enable. */
const int target_disable; /* Target flags to disable. */
+ const int target_isa_enable; /* Target isa flags to enable. */
+ const int target_isa_disable; /* Target isa flags to disable. */
const int align_loop; /* Default alignments. */
const int align_loop_max_skip;
const int align_jump;
@@ -1657,20 +1660,20 @@ override_options (void)
}
const processor_target_table[PROCESSOR_max] =
{
- {&i386_cost, 0, 0, 4, 3, 4, 3, 4},
- {&i486_cost, 0, 0, 16, 15, 16, 15, 16},
- {&pentium_cost, 0, 0, 16, 7, 16, 7, 16},
- {&pentiumpro_cost, 0, 0, 16, 15, 16, 7, 16},
- {&geode_cost, 0, 0, 0, 0, 0, 0, 0},
- {&k6_cost, 0, 0, 32, 7, 32, 7, 32},
- {&athlon_cost, 0, 0, 16, 7, 16, 7, 16},
- {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0},
- {&k8_cost, 0, 0, 16, 7, 16, 7, 16},
- {&nocona_cost, 0, 0, 0, 0, 0, 0, 0},
- {&core2_cost, 0, 0, 16, 7, 16, 7, 16},
- {&generic32_cost, 0, 0, 16, 7, 16, 7, 16},
- {&generic64_cost, 0, 0, 16, 7, 16, 7, 16},
- {&amdfam10_cost, 0, 0, 32, 24, 32, 7, 32}
+ {&i386_cost, 0, 0, 0, 0, 4, 3, 4, 3, 4},
+ {&i486_cost, 0, 0, 0, 0, 16, 15, 16, 15, 16},
+ {&pentium_cost, 0, 0, 0, 0, 16, 7, 16, 7, 16},
+ {&pentiumpro_cost, 0, 0, 0, 0, 16, 15, 16, 7, 16},
+ {&geode_cost, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {&k6_cost, 0, 0, 0, 0, 32, 7, 32, 7, 32},
+ {&athlon_cost, 0, 0, 0, 0, 16, 7, 16, 7, 16},
+ {&pentium4_cost, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {&k8_cost, 0, 0, 0, 0, 16, 7, 16, 7, 16},
+ {&nocona_cost, 0, 0, 0, 0, 0, 0, 0, 0, 0},
+ {&core2_cost, 0, 0, 0, 0, 16, 7, 16, 7, 16},
+ {&generic32_cost, 0, 0, 0, 0, 16, 7, 16, 7, 16},
+ {&generic64_cost, 0, 0, 0, 0, 16, 7, 16, 7, 16},
+ {&amdfam10_cost, 0, 0, 0, 0, 32, 24, 32, 7, 32}
};
static const char * const cpu_names[] = TARGET_CPU_DEFAULT_NAMES;
@@ -1925,9 +1928,9 @@ override_options (void)
if ((TARGET_64BIT == 0) != (ix86_cmodel == CM_32))
error ("code model %qs not supported in the %s bit mode",
ix86_cmodel_string, TARGET_64BIT ? "64" : "32");
- if ((TARGET_64BIT != 0) != ((target_flags & MASK_64BIT) != 0))
+ if ((TARGET_64BIT != 0) != ((target_isa_flags & MASK_64BIT) != 0))
sorry ("%i-bit mode not compiled in",
- (target_flags & MASK_64BIT) ? 64 : 32);
+ (target_isa_flags & MASK_64BIT) ? 64 : 32);
for (i = 0; i < pta_size; i++)
if (! strcmp (ix86_arch_string, processor_alias_table[i].name))
@@ -1936,29 +1939,29 @@ override_options (void)
/* Default cpu tuning to the architecture. */
ix86_tune = ix86_arch;
if (processor_alias_table[i].flags & PTA_MMX
- && !(target_flags_explicit & MASK_MMX))
- target_flags |= MASK_MMX;
+ && !(target_isa_flags_explicit & MASK_MMX))
+ target_isa_flags |= MASK_MMX;
if (processor_alias_table[i].flags & PTA_3DNOW
- && !(target_flags_explicit & MASK_3DNOW))
- target_flags |= MASK_3DNOW;
+ && !(target_isa_flags_explicit & MASK_3DNOW))
+ target_isa_flags |= MASK_3DNOW;
if (processor_alias_table[i].flags & PTA_3DNOW_A
- && !(target_flags_explicit & MASK_3DNOW_A))
- target_flags |= MASK_3DNOW_A;
+ && !(target_isa_flags_explicit & MASK_3DNOW_A))
+ target_isa_flags |= MASK_3DNOW_A;
if (processor_alias_table[i].flags & PTA_SSE
- && !(target_flags_explicit & MASK_SSE))
- target_flags |= MASK_SSE;
+ && !(target_isa_flags_explicit & MASK_SSE))
+ target_isa_flags |= MASK_SSE;
if (processor_alias_table[i].flags & PTA_SSE2
- && !(target_flags_explicit & MASK_SSE2))
- target_flags |= MASK_SSE2;
+ && !(target_isa_flags_explicit & MASK_SSE2))
+ target_isa_flags |= MASK_SSE2;
if (processor_alias_table[i].flags & PTA_SSE3
- && !(target_flags_explicit & MASK_SSE3))
- target_flags |= MASK_SSE3;
+ && !(target_isa_flags_explicit & MASK_SSE3))
+ target_isa_flags |= MASK_SSE3;
if (processor_alias_table[i].flags & PTA_SSSE3
- && !(target_flags_explicit & MASK_SSSE3))
- target_flags |= MASK_SSSE3;
+ && !(target_isa_flags_explicit & MASK_SSSE3))
+ target_isa_flags |= MASK_SSSE3;
if (processor_alias_table[i].flags & PTA_SSE4_1
- && !(target_flags_explicit & MASK_SSE4_1))
- target_flags |= MASK_SSE4_1;
+ && !(target_isa_flags_explicit & MASK_SSE4_1))
+ target_isa_flags |= MASK_SSE4_1;
if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
x86_prefetch_sse = true;
if (processor_alias_table[i].flags & PTA_CX16)
@@ -1970,8 +1973,8 @@ override_options (void)
&& !(target_flags_explicit & MASK_ABM))
target_flags |= MASK_ABM;
if (processor_alias_table[i].flags & PTA_SSE4A
- && !(target_flags_explicit & MASK_SSE4A))
- target_flags |= MASK_SSE4A;
+ && !(target_isa_flags_explicit & MASK_SSE4A))
+ target_isa_flags |= MASK_SSE4A;
if (!(TARGET_64BIT && (processor_alias_table[i].flags & PTA_NO_SAHF)))
x86_sahf = true;
if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
@@ -2027,7 +2030,9 @@ override_options (void)
else
ix86_cost = processor_target_table[ix86_tune].cost;
target_flags |= processor_target_table[ix86_tune].target_enable;
+ target_isa_flags |= processor_target_table[ix86_tune].target_isa_enable;
target_flags &= ~processor_target_table[ix86_tune].target_disable;
+ target_isa_flags &= ~processor_target_table[ix86_tune].target_isa_disable;
/* Arrange to set up i386_stack_locals for all functions. */
init_machine_status = ix86_init_machine_status;
@@ -2166,34 +2171,34 @@ override_options (void)
/* Turn on SSSE3 builtins for -msse4.1. */
if (TARGET_SSE4_1)
- target_flags |= MASK_SSSE3;
+ target_isa_flags |= MASK_SSSE3;
/* Turn on SSE3 builtins for -mssse3. */
if (TARGET_SSSE3)
- target_flags |= MASK_SSE3;
+ target_isa_flags |= MASK_SSE3;
/* Turn on SSE3 builtins for -msse4a. */
if (TARGET_SSE4A)
- target_flags |= MASK_SSE3;
+ target_isa_flags |= MASK_SSE3;
/* Turn on SSE2 builtins for -msse3. */
if (TARGET_SSE3)
- target_flags |= MASK_SSE2;
+ target_isa_flags |= MASK_SSE2;
/* Turn on SSE builtins for -msse2. */
if (TARGET_SSE2)
- target_flags |= MASK_SSE;
+ target_isa_flags |= MASK_SSE;
/* Turn on MMX builtins for -msse. */
if (TARGET_SSE)
{
- target_flags |= MASK_MMX & ~target_flags_explicit;
+ target_isa_flags |= MASK_MMX & ~target_isa_flags_explicit;
x86_prefetch_sse = true;
}
/* Turn on MMX builtins for 3Dnow. */
if (TARGET_3DNOW)
- target_flags |= MASK_MMX;
+ target_isa_flags |= MASK_MMX;
/* Turn on POPCNT builtins for -mabm. */
if (TARGET_ABM)
@@ -2207,9 +2212,10 @@ override_options (void)
/* Enable by default the SSE and MMX builtins. Do allow the user to
explicitly disable any of these. In particular, disabling SSE and
MMX for kernel code is extremely useful. */
- target_flags
- |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | TARGET_SUBTARGET64_DEFAULT)
- & ~target_flags_explicit);
+ target_isa_flags
+ |= ((MASK_SSE2 | MASK_SSE | MASK_MMX | TARGET_ISA_SUBTARGET64_DEFAULT)
+ & ~target_isa_flags_explicit);
+ target_flags |= TARGET_SUBTARGET64_DEFAULT & ~target_flags_explicit;
}
else
{
@@ -16519,7 +16525,7 @@ enum ix86_builtins
static GTY(()) tree ix86_builtins[(int) IX86_BUILTIN_MAX];
/* Add a ix86 target builtin function with CODE, NAME and TYPE. Do so,
- * if the target_flags include one of MASK. Stores the function decl
+ * if the target_isa_flags include one of MASK. Stores the function decl
* in the ix86_builtins array.
* Returns the function decl or NULL_TREE, if the builtin was not added. */
@@ -16528,7 +16534,7 @@ def_builtin (int mask, const char *name,
{
tree decl = NULL_TREE;
- if (mask & target_flags
+ if (mask & target_isa_flags
&& (!(mask & MASK_64BIT) || TARGET_64BIT))
{
decl = add_builtin_function (name, type, code, BUILT_IN_MD,
@@ -22622,7 +22628,6 @@ static const struct attribute_spec ix86_
#undef TARGET_DEFAULT_TARGET_FLAGS
#define TARGET_DEFAULT_TARGET_FLAGS \
(TARGET_DEFAULT \
- | TARGET_64BIT_DEFAULT \
| TARGET_SUBTARGET_DEFAULT \
| TARGET_TLS_DIRECT_SEG_REFS_DEFAULT)
--- gcc/config/i386/i386.h.isa 2007-05-22 10:58:08.000000000 -0700
+++ gcc/config/i386/i386.h 2007-05-23 14:09:01.000000000 -0700
@@ -376,6 +376,9 @@ extern int x86_prefetch_sse;
/* Extra bits to force on w/ 64-bit mode. */
#define TARGET_SUBTARGET64_DEFAULT 0
+/* Extra isa bits to force on w/ 64-bit mode. */
+#define TARGET_ISA_SUBTARGET64_DEFAULT TARGET_64BIT_DEFAULT
+
/* This is not really a target flag, but is done this way so that
it's analogous to similar code for Mach-O on PowerPC. darwin.h
redefines this to 1. */
--- gcc/config/i386/i386.opt.isa 2007-05-22 10:58:08.000000000 -0700
+++ gcc/config/i386/i386.opt 2007-05-23 14:00:04.000000000 -0700
@@ -23,18 +23,6 @@ m128bit-long-double
Target RejectNegative Report Mask(128BIT_LONG_DOUBLE)
sizeof(long double) is 16
-m32
-Target RejectNegative Negative(m64) Report InverseMask(64BIT)
-Generate 32bit i386 code
-
-m3dnow
-Target Report Mask(3DNOW)
-Support 3DNow! built-in functions
-
-m64
-Target RejectNegative Negative(m32) Report Mask(64BIT)
-Generate 64bit x86-64 code
-
m80387
Target Report Mask(80387)
Use hardware fp
@@ -119,10 +107,6 @@ mintel-syntax
Target Undocumented
;; Deprecated
-mmmx
-Target Report Mask(MMX)
-Support MMX built-in functions
-
mms-bitfields
Target Report Mask(MS_BITFIELD_LAYOUT)
Use native (MS) bitfield layout
@@ -171,30 +155,6 @@ msoft-float
Target InverseMask(80387)
Do not use hardware fp
-msse
-Target Report Mask(SSE)
-Support MMX and SSE built-in functions and code generation
-
-msse2
-Target Report Mask(SSE2)
-Support MMX, SSE and SSE2 built-in functions and code generation
-
-msse3
-Target Report Mask(SSE3)
-Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
-
-mssse3
-Target Report Mask(SSSE3)
-Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
-
-msse4.1
-Target Report Mask(SSE4_1)
-Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
-
-msse4a
-Target Report Mask(SSE4A)
-Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
-
mpopcnt
Target Report Mask(POPCNT)
Support code generation of popcnt instruction for popcount built-ins
@@ -242,6 +202,3 @@ Use direct references against %gs when a
mtune=
Target RejectNegative Joined Var(ix86_tune_string)
Schedule code for given CPU
-
-;; Support Athlon 3Dnow builtins
-Mask(3DNOW_A)
--- gcc/config/i386/isa.opt.isa 2007-05-23 10:32:59.000000000 -0700
+++ gcc/config/i386/isa.opt 2007-05-23 14:22:52.000000000 -0700
@@ -0,0 +1,63 @@
+; ISA options for the IA-32 and AMD64 ports of the compiler.
+
+; Copyright (C) 2007 Free Software Foundation, Inc.
+;
+; This file is part of GCC.
+;
+; GCC is free software; you can redistribute it and/or modify it under
+; the terms of the GNU General Public License as published by the Free
+; Software Foundation; either version 2, or (at your option) any later
+; version.
+;
+; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
+; WARRANTY; without even the implied warranty of MERCHANTABILITY or
+; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+; for more details.
+;
+; You should have received a copy of the GNU General Public License
+; along with GCC; see the file COPYING. If not, write to the Free
+; Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
+; 02110-1301, USA.
+
+m32
+Target RejectNegative Negative(m64) Report InverseMask(64BIT) Var(target_isa_flags)
+Generate 32bit i386 code
+
+m64
+Target RejectNegative Negative(m32) Report Mask(64BIT) Var(target_isa_flags) Init(TARGET_64BIT_DEFAULT)
+Generate 64bit x86-64 code
+
+m3dnow
+Target Report Mask(3DNOW) Var(target_isa_flags)
+Support 3DNow! built-in functions
+
+mmmx
+Target Report Mask(MMX) Var(target_isa_flags)
+Support MMX built-in functions
+
+msse
+Target Report Mask(SSE) Var(target_isa_flags)
+Support MMX and SSE built-in functions and code generation
+
+msse2
+Target Report Mask(SSE2) Var(target_isa_flags)
+Support MMX, SSE and SSE2 built-in functions and code generation
+
+msse3
+Target Report Mask(SSE3) Var(target_isa_flags)
+Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
+
+mssse3
+Target Report Mask(SSSE3) Var(target_isa_flags)
+Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
+
+msse4.1
+Target Report Mask(SSE4_1) Var(target_isa_flags)
+Support MMX, SSE, SSE2, SSE3, SSSE3 and SSE4.1 built-in functions and code generation
+
+msse4a
+Target Report Mask(SSE4A) Var(target_isa_flags)
+Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
+
+;; Support Athlon 3Dnow builtins
+Target Mask(3DNOW_A) Var(target_isa_flags) Undocumented
--- gcc/config/linux.h.isa 2007-03-08 08:49:19.000000000 -0800
+++ gcc/config/linux.h 2007-05-23 12:16:48.000000000 -0700
@@ -125,9 +125,9 @@ Boston, MA 02110-1301, USA. */
/* Determine whether the entire c99 runtime
is present in the runtime library. */
-#define TARGET_C99_FUNCTIONS (OPTION_GLIBC)
+#define TARGET_C99_FUNCTIONS (TARGET_GLIBC)
/* Whether we have sincos that follows the GNU extension. */
-#define TARGET_HAS_SINCOS (OPTION_GLIBC)
+#define TARGET_HAS_SINCOS (TARGET_GLIBC)
#define TARGET_POSIX_IO
--- gcc/config/linux.opt.isa 2006-11-18 06:26:22.000000000 -0800
+++ gcc/config/linux.opt 2007-05-23 12:48:50.000000000 -0700
@@ -21,7 +21,7 @@
; 02110-1301, USA.
muclibc
-Target RejectNegative Report Mask(UCLIBC) Var(linux_uclibc) Init(UCLIBC_DEFAULT ? OPTION_MASK_UCLIBC : 0)
+Target RejectNegative Report Mask(UCLIBC) Var(linux_uclibc) Init(UCLIBC_DEFAULT ? MASK_UCLIBC : 0)
Use uClibc instead of GNU libc
mglibc
--- gcc/opt-functions.awk.isa 2007-02-12 09:52:44.000000000 -0800
+++ gcc/opt-functions.awk 2007-05-23 13:06:42.000000000 -0700
@@ -138,16 +138,24 @@ function var_set(flags)
s = opt_args("Mask", flags);
if (s != "") {
vn = var_name(flags);
- if (vn)
- return "CLVC_BIT_SET, OPTION_MASK_" s
+ if (vn) {
+ if (flag_target_mask_p(flags))
+ return "CLVC_BIT_SET, MASK_" s
+ else
+ return "CLVC_BIT_SET, OPTION_MASK_" s
+ }
else
return "CLVC_BIT_SET, MASK_" s
}
s = nth_arg(0, opt_args("InverseMask", flags));
if (s != "") {
vn = var_name(flags);
- if (vn)
- return "CLVC_BIT_CLEAR, OPTION_MASK_" s
+ if (vn) {
+ if (flag_target_mask_p(flags))
+ return "CLVC_BIT_CLEAR, MASK_" s
+ else
+ return "CLVC_BIT_CLEAR, OPTION_MASK_" s
+ }
else
return "CLVC_BIT_CLEAR, MASK_" s
}
@@ -156,16 +164,29 @@ function var_set(flags)
return "CLVC_BOOLEAN, 0"
}
+# Return nonzero if an option with flags FLAGS is a target flag with
+# mask.
+function flag_target_mask_p(flags)
+{
+ return flag_set_p("Target", flags) && (opt_args("Mask", flags) != "" || opt_args("InverseMask", flags) != "")
+}
+
# Given that an option called NAME has flags FLAGS, return an initializer
-# for the "flag_var" field of its cl_options[] entry.
+# for the "flag_var" and "flag_explicit" fields of its cl_options[] entry.
function var_ref(name, flags)
{
name = var_name(flags) static_var(name, flags)
- if (name != "")
- return "&" name
- if (opt_args("Mask", flags) != "")
- return "&target_flags"
- if (opt_args("InverseMask", flags) != "")
- return "&target_flags"
- return "0"
+ if (name == "") {
+ if (opt_args("Mask", flags) != "")
+ name = "target_flags"
+ else if (opt_args("InverseMask", flags) != "")
+ name = "target_flags"
+ }
+ if (name != "") {
+ if (flag_target_mask_p(flags))
+ return "&" name ", &" name "_explicit"
+ else
+ return "&" name ", 0"
+ }
+ return "0, 0"
}
--- gcc/optc-gen.awk.isa 2007-02-12 09:52:44.000000000 -0800
+++ gcc/optc-gen.awk 2007-05-23 12:56:40.000000000 -0700
@@ -62,15 +62,19 @@ for (i = 1; i <= n_headers; i++)
print "#include " quote "opts.h" quote
print "#include " quote "intl.h" quote
print ""
-print "#ifdef GCC_DRIVER"
-print "int target_flags;"
-print "#endif /* GCC_DRIVER */"
-print ""
for (i = 0; i < n_opts; i++) {
name = var_name(flags[i]);
- if (name == "")
- continue;
+ if (name == "") {
+ if (flag_target_mask_p(flags[i])) {
+ name = "target_flags"
+ type = "int "
+ }
+ else
+ continue;
+ }
+ else
+ type = var_type(flags[i])
if (flag_set_p("VarExists", flags[i])) {
# Need it for the gcc driver.
@@ -92,7 +96,9 @@ for (i = 0; i < n_opts; i++) {
print "#ifdef GCC_DRIVER"
print "/* Set by -" opts[i] "."
print " " help[i] " */"
- print var_type(flags[i]) name init ";"
+ print type name init ";"
+ if (flag_target_mask_p(flags[i]))
+ print type name "_explicit;"
if (gcc_driver == 1)
print "#endif /* GCC_DRIVER */"
print ""
--- gcc/opth-gen.awk.isa 2007-03-08 08:49:20.000000000 -0800
+++ gcc/opth-gen.awk 2007-05-23 13:08:32.000000000 -0700
@@ -60,25 +60,38 @@ print ""
print "#ifndef OPTIONS_H"
print "#define OPTIONS_H"
print ""
-print "extern int target_flags;"
-print ""
for (i = 0; i < n_opts; i++) {
name = var_name(flags[i]);
- if (name == "")
- continue;
+ if (name == "") {
+ if (flag_target_mask_p(flags[i])) {
+ name = "target_flags"
+ type = "int "
+ }
+ else
+ continue;
+ }
+ else
+ type = var_type(flags[i])
+
+ if (name in var_seen)
+ continue
- print "extern " var_type(flags[i]) name ";"
+ print "extern " type name ";"
+ if (flag_target_mask_p(flags[i]))
+ print "extern " type name "_explicit;"
+
+ var_seen[name] = 1;
}
print ""
for (i = 0; i < n_opts; i++) {
name = opt_args("Mask", flags[i])
vname = var_name(flags[i])
- mask = "MASK_"
- if (vname != "") {
+ if (vname == "" || flag_target_mask_p(flags[i]))
+ mask = "MASK_"
+ else
mask = "OPTION_MASK_"
- }
if (name != "" && !flag_set_p("MaskExists", flags[i]))
print "#define " mask name " (1 << " masknum[vname]++ ")"
}
@@ -99,13 +112,19 @@ print ""
for (i = 0; i < n_opts; i++) {
name = opt_args("Mask", flags[i])
vname = var_name(flags[i])
- macro = "OPTION_"
- mask = "OPTION_MASK_"
if (vname == "") {
vname = "target_flags"
macro = "TARGET_"
mask = "MASK_"
}
+ else if (flag_target_mask_p(flags[i])) {
+ macro = "TARGET_"
+ mask = "MASK_"
+ }
+ else {
+ macro = "OPTION_"
+ mask = "OPTION_MASK_"
+ }
if (name != "" && !flag_set_p("MaskExists", flags[i]))
print "#define " macro name \
" ((" vname " & " mask name ") != 0)"
@@ -120,13 +139,19 @@ for (i = 0; i < n_opts; i++) {
opt = opt_args("InverseMask", flags[i])
if (opt ~ ",") {
vname = var_name(flags[i])
- macro = "OPTION_"
- mask = "OPTION_MASK_"
if (vname == "") {
vname = "target_flags"
macro = "TARGET_"
mask = "MASK_"
}
+ else if (flag_target_mask_p(flags[i])) {
+ macro = "TARGET_"
+ mask = "MASK_"
+ }
+ else {
+ macro = "OPTION_"
+ mask = "OPTION_MASK_"
+ }
print "#define " macro nth_arg(1, opt) \
" ((" vname " & " mask nth_arg(0, opt) ") == 0)"
}
--- gcc/opts.c.isa 2007-05-23 10:32:59.000000000 -0700
+++ gcc/opts.c 2007-05-23 10:59:47.000000000 -0700
@@ -566,10 +566,8 @@ handle_option (const char **argv, unsign
*(int *) option->flag_var |= option->var_value;
else
*(int *) option->flag_var &= ~option->var_value;
- if (option->flag_var == &target_flags)
- target_flags_explicit |= option->var_value;
- else if (option->flag_var == &target_isa_flags)
- target_isa_flags_explicit |= option->var_value;
+ if (option->flag_explicit_var)
+ *(int *) option->flag_explicit_var |= option->var_value;
break;
case CLVC_STRING:
--- gcc/opts.h.isa 2007-02-25 17:26:27.000000000 -0800
+++ gcc/opts.h 2007-05-23 11:58:45.000000000 -0700
@@ -49,6 +49,7 @@ struct cl_option
int neg_index;
unsigned int flags;
void *flag_var;
+ void *flag_explicit_var;
enum cl_var_type var_type;
int var_value;
};
--- gcc/rtlanal.c.isa 2007-05-23 05:29:34.000000000 -0700
+++ gcc/rtlanal.c 2007-05-23 11:03:10.000000000 -0700
@@ -78,12 +78,6 @@ static unsigned int num_sign_bit_copies1
-1 if a code has no such operand. */
static int non_rtx_starting_operands[NUM_RTX_CODE];
-/* Bit flags that specify the machine subtype we are compiling for.
- Bits are tested using macros TARGET_... defined in the tm.h file
- and set by `-m...' switches. Must be defined in rtlanal.c. */
-
-int target_flags;
-
/* Truncation narrows the mode from SOURCE mode to DESTINATION mode.
If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is
SIGN_EXTEND then while narrowing we also have to enforce the
--- gcc/toplev.c.isa 2007-05-18 14:53:31.000000000 -0700
+++ gcc/toplev.c 2007-05-23 11:02:37.000000000 -0700
@@ -177,17 +177,6 @@ const char *dump_base_name;
const char *aux_base_name;
-/* Bit flags that specify the machine subtype we are compiling for.
- Bits are tested using macros TARGET_... defined in the tm.h file
- and set by `-m...' switches. Must be defined in rtlanal.c. */
-
-extern int target_flags;
-
-/* A mask of target_flags that includes bit X if X was set or cleared
- on the command line. */
-
-int target_flags_explicit;
-
/* Debug hooks - dependent upon command line options. */
const struct gcc_debug_hooks *debug_hooks;
--- gcc/toplev.h.isa 2007-03-14 07:46:59.000000000 -0700
+++ gcc/toplev.h 2007-05-23 11:01:02.000000000 -0700
@@ -112,8 +112,6 @@ extern const char *aux_info_file_name;
extern const char *asm_file_name;
extern bool exit_after_options;
-extern int target_flags_explicit;
-
/* True if the user has tagged the function with the 'section'
attribute. */