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Re: PATCH: Add SSE4.1 support
On Fri, Apr 20, 2007 at 12:56:42PM -0700, Richard Henderson wrote:
> On Fri, Apr 20, 2007 at 12:00:59PM -0700, H. J. Lu wrote:
> > There is one issue remaining: we like to use
> >
> > movX xxm, reg
> >
> > instead
> >
> > movX xmm, mem; mov mem, reg
> >
> > and
> >
> > extract $0, xmm, reg
> >
> > But "movX xxm, reg" is only enabled by TARGET_INTER_UNIT_MOVES, which
> > is disabled by default.
>
> Pretty much by definition you *don't* want to generate either
> of these if TARGET_INTER_UNIT_MOVES is false, since these *are*
> inter-unit moves. Duh.
>
> > However, we don't want to turn on TARGET_INTER_UNIT_MOVES by default.
>
> But it *is* enabled for the Intel chips that you care about,
> so I don't see the problem.
>
> > Should I add a new option something
> > like, TARGET_SSE_TO_GENERAL_REG_MOVE or allow "movX xxm, reg"
> > unconditionally?
>
> Absolutely not. Why should you do anything at all?
TARGET_INTER_UNIT_MOVES controls moving from gr to xxm and moving
from xxm to gr. We may not want "mov gr, xmm". But "mov xmm, gr"
is always a win, comparing with moving through memory, espeically
when xmm is a vector of gr.
H.J.