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> Jan Hubicka wrote: > >>+@item -mcmpxchg16b > >>+@opindex -mcmpxchg16b > >>+This option will enable GCC to use CMPXCHG16B instruction in generated > >>code.
If the patch is not commited yet, perhaps > +This option will enable GCC to use SAHF instruction in generated code. Early > +Intel CPUs with Intel 64 lacked LAHF and SAHF instructions supported by AMD64 > +until introduction of Pentium 4 G1 step in December 2005. LAHF and SAHF are > +load and store instructions, respectively, for certain status flags. These > +instructions are used for virtualization and floating-point condition handling.
I would leave out the virtualization - GCC won't use it in this context so it is a bit misleading. It might be nice to make clear that sahf use is very limited, since fcomi can be used in wast majority cases. But this is all just nitpicking.
Thanks, Uros.
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