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Re: more tidying of x86 feature tests
> > On 3/6/07, Jan Hubicka <hubicka@ucw.cz> wrote:
> >
> > >> >+ /* ??? Any idea why this is unconditionally disabled for 64-bit? */
> > >> >+ if (TARGET_64BIT)
> > >> >+ TARGET_USE_SAHF = 0;
> > >>
> > >> IIRC, early x86_64 ISA draft didn't have SAHF and some prototypes didn't
> > >> handle this insn.
> > >>
> > >> At least for AMD, there is no need to disable this, as sahf is
> > >> DirectPath latency 1 insn.
> > >
> > >My recollection is that while AMD chips accepts SAHF, Intel chips
> > >originally didn't accept SAHF and new P4s and Cores does.
> > >At least wikipedia claims:
> > >
> > >Early Intel CPUs with Intel 64 lacked LAHF and SAHF instructions
> > >supported by AMD64 until introduction of Pentium 4 G1 step in December
> > >2005. LAHF and SAHF are load and store instructions, respectively, for
> > >certain status flags. These instructions are used for virtualization and
> > >floating-point condition handling.
> > >
> > >So I guess the conditional above can be enabled iff we are 64bit and
> > >arch is specified as "x86-64" or "nocona"
> >
> > Attached patch implements this proposal.
> >
> > 2007-03-07 Uros Bizjak <ubizjak@gmail.com>
> >
> > * config/i386/i386.c (ix86_tune_features) [X86_TUNE_SAHF]:
> > Also enable for m_K8 and m_AMDFAM10.
> > (override_options): Do not unconditionally disable
> > TARGET_USE_SAHF for 64-bit.
> > * config/i386/i386.md (x86_sahf_1): Do not disable for
> > TARGET_64BIT.
> >
> > Patch was tested on i686-pc-linux-gnu. If there are no objections,
> > I'll commit this patch to SVN shortly.
>
> I think your patch enables the SAHF for Nocona, that is wrong. For
> Nocona we need to enable it in 32bit mode and disable in 64bit mode
> (unless we want to split Noconas into early and late models).
And also the fact whether SAHF is preferred should depend on -mtune
switch, whether it is available in the ISA should depend on -march
switch.
Honza
>
> Honza
> >
> > Uros.
> > >
> > >Honza
> > >>
> > >> Uros.
> > >>
> > >
>