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Re: [patch] tuning gcc for AMDFAM10 processor (patch 1)
- From: Andi Kleen <ak at suse dot de>
- To: "Jagasia, Harsha" <harsha dot jagasia at amd dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: 30 Jan 2007 06:43:34 +0100
- Subject: Re: [patch] tuning gcc for AMDFAM10 processor (patch 1)
- References: <D5B24B5251882048AD03DDFA431BB79059CF03@SAUSEXMB3.amd.com.suse.lists.egcs-patches>
"Jagasia, Harsha" <harsha.jagasia@amd.com> writes:
> This is the 1st of 11 patches to tune gcc for AMD's AMDFAM10 processor
> (based on mainline rev 121295). This patch defines march=amdfam10 and
> adds built-ins and intrinsics for the new instructions as needed.
>+#ifdef __x86_64__
>+ __asm__ ("pushq %%rcx; pushq %%rbx; cpuid; popq %%rbx; popq %%rcx"
>+ : "=a" (fl1) : "0" (0x80000000) : "rdx", "cc");
>+#else
>+ __asm__ ("pushl %%ecx; pushl %%ebx; cpuid; popl %%ebx; popl %%ecx"
>+ : "=a" (fl1) : "0" (0x80000000) : "edx", "cc");
>+#endif
You could do without the ifdef when you put ecx,ebx,edx into the clobber
list (32bit clobber implies 64bit one on x86-64)
Also I didn't think either push/pop nor cpuid changed cc.
Also I was wondering how hard it would be to make gcc detect code
patterns automatically for the new bitfield instructions?
-Andi