This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] Fix PR middle-end/28690, indexed load/store performance + reload bug

On Wed, 2006-12-06 at 22:27 +0100, Ulrich Weigand wrote:
> So to get back to my original question: can you verify that it is in fact
> the code in the second half of the "if" I quoted in the earlier message
> that causes eliminate_regs_in_insn to replace just the one occurrance of
> the eliminable sfp register and then immediately return?

Sorry for misunderstanding you. Yes, we do drop into the second half of
that if and we only update the "update" pattern and then jump to "done"
without updating the "load" pattern.

> The solution would return an insn containing only the
>             (set (reg/f:SI 9 9 [orig:124 D.966 ] [124])
>                 (plus:SI (reg/f:SI 1 1)
>                     (const_int 8 [0x8])))
> part, which would subsequently cause an addi instruction to be
> generated.  Since there isn't any match_dup any more, that failure
> mode cannot apply any longer.

Ok, sounds good to me.  Do you have a recommendation on how we can
achieve that?


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]