Re: [PATCH] Fix PR middle-end/28690, indexed load/store performance + reload bug

[Peter Bergner <bergner at vnet dot ibm dot com>]

On Tue, 2006-12-05 at 11:31 -0600, Peter Bergner wrote:
> On Tue, 2006-12-05 at 14:04 +0100, Ulrich Weigand wrote:
> > I'm not sure about this change.  I'm afraid on platforms where
> > add instructions are usually a PARALLEL (with a clobber of the
> > condition code register), the change may cause eliminate_regs_in_insn
> > to miss instructions that *set* an eliminable register (what the
> > loop immediately following the above lines tries to find).
> > I'd expect this to cause problems e.g. on s390 ..
> 
> Then how about a scheme where we continue to call single_set() as
> we do now.  However, if single_set() returns non null and the insn
> is a PARALLEL, then we recursively call eliminate_regs_in_insn() for
> the portion(s) of the PARALLEL not returned by single_set()?  That would
> allow this portion of the code to behave as before, while allowing
> the unused portion of the PARALLEL to have it's regs eliminated.

Well, we can't just recursively call eliminate_regs_in_insn(), since
it expects an insn and doesn't like seeing a pattern instead.  I'll
try cooking up some code that conceptually does that without actually
doing the recursive call.

Peter