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Re: [PATCH, i386]: Insert "cld" via optimize mode switching
On 12/1/06, Richard Guenther <richard.guenther@gmail.com> wrote:
> Attached patch optimizes insertion of "cld" instruction via optimize
> mode switching pass.
>
> "Original" insn pattern, as emitted by expanders, is splitted just
> before mode switching pass into "fake" cld insn pattern "(use (reg:SI
> DIRFLAG_REG))", which has the sole purpose of showing its "cld" type
> attribute during o_m_s pass. The "real" instruction is generated as
> "cld_1" insn pattern during optimize_mode_switching pass at its optimal
> position. Although fake cld instructions remain present in insn flow,
> they don't emit anything into *.s files. Mode is reset to UNINTIALIZED
> after every call and asm insn pattern.
Hmm, do we or the ABI guarantee to save/restore the necessary state
on entry/exit of signal handlers? So, is this optimization safe for
synchronous signals and/or exceptions?
There is nothing specified by ABI, this is why all rep prefixed
instructions require direction bit setting to be known. This patch
looks for the optimization opportunity, where cld insn is used inside
loop or where cld is emmitted twice in a row due to two consecutive
string operations in a BB.
Regarding signal handlers - this optimization is the same as FP
rounding mode setting optimizaton. It uses CPU mode switching
infrastructure (mode_switching.c), and is up to this infrastructure to
handle abnormal edges (it does, please grep for "abnormal" in
mode_switching.c). Until now, it handled x87 FP rounding modes without
problems ;)
Uros.