Re: [PATCH] [testsuite+spu] enable vectorizer testuite for the SPU

[Andrew Pinski <pinskia at gmail dot com>]

On Fri, 2006-12-01 at 11:27 +0200, Dorit Nuzman wrote:
> 
> Index: config/spu/spu.md
> ===================================================================
> --- config/spu/spu.md   (revision 119101)
> +++ config/spu/spu.md   (working copy)
> @@ -3169,3 +3169,31 @@
>  ;;
>  (include "spu-builtins.md")
>  
> +  
> +(define_expand "smaxv4sf3"
> +  [(set (match_operand:V4SF 0 "register_operand" "=r")
> +        (smax:V4SF (match_operand:V4SF 1 "register_operand" "r")
> +                 (match_operand:V4SF 2 "register_operand" "r")))]
> +  ""
> +  "
> +{
> +  rtx mask = gen_reg_rtx (V4SImode);
> +
> +  emit_insn (gen_cgt_v4sf (mask, operands[1], operands[2]));
> +  emit_insn (gen_selb (operands[0], operands[2], operands[1], mask));
> +  DONE;
> +}") 
> +
> +(define_expand "sminv4sf3"
> +  [(set (match_operand:V4SF 0 "register_operand" "=r")
> +        (smax:V4SF (match_operand:V4SF 1 "register_operand" "r")
> +                 (match_operand:V4SF 2 "register_operand" "r")))]
> +  ""
> +  "
> +{
> +  rtx mask = gen_reg_rtx (V4SImode);
> +
> +  emit_insn (gen_cgt_v4sf (mask, operands[1], operands[2]));
> +  emit_insn (gen_selb (operands[0], operands[1], operands[2], mask));
> +  DONE;
> +}")  

This part is OK with the appropriate changelog.

For:

> (5) testcases that require double-precision-fp conditional operations.
> I
> added a keyword for targets that don't support this, and xfailed this
> test
> for those targets:
> 
> FAIL: gcc.dg/vect/fast-math-vect-reduc-7.c scan-tree-dump-times
> vectorized
> 3 loops 1

There is a vector version of the compare function that is defined by the
"SIMD Math library for the Cell BEA" so we should be able to use that
later on.


Thanks,
Andrew Pinski