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Re: [patch] MIPS: 64bit floating point support for MIPS32R2

Richard Sandiford <> writes:
> David Ung <> writes:
>> Richard Sandiford wrote:
>>> David Ung <> writes:
>> <snip>
>>>>Index: gcc/gcc/gcc/config/mips/mips.h
>>>>--- gcc.orig/gcc/gcc/config/mips/mips.h 2006-11-06 17:20:29.000000000 +0000
>>>>+++ gcc/gcc/gcc/config/mips/mips.h      2006-11-06 17:39:00.000000000 +0000
>>>>@@ -611,6 +611,7 @@
>>>>     FP madd and msub instructions, and the FP recip and recip sqrt
>>>>     instructions.  */
>>>>  #define ISA_HAS_FP4             ((ISA_MIPS4                            \
>>>>+                                 || (ISA_MIPS32R2 && TARGET_FLOAT64)   \
>>>>                                   || ISA_MIPS64)                        \
>>>>                                  && !TARGET_MIPS16)
>>> This looks odd.  The macro controls things like madd.<fmt> and
>>> recip.<fmt>.  Are those insns really only available if TARGET_FLOAT64?
>>> V2.50 of the MIPS32r2 architecture manual suggests that the .s and .d
>>> forms are available even in "16 FP registers mode"; the only exception
>>> given is .ps, which we would never use unless TARGET_FLOAT64 anyway.
>> Well, if you look at the section "Restrictions" last sentence.  ".. if
>> access to 64-bit floating point operations is not enabled, a Reserved
>> Instruction Exceptions is signaled."  And again under "Operations".
>> Basically, one of the status bits needs to be turn on to enable the
>> 64bit fpu (which reminds me that I need to send a patch for libgloss).
> I believe you, but which instruction are you looking at?  I don't see
> that text for madd, for instance.  Just the:
>     The result of MADD.PS is UNPREDICTABLE if the processor is executing
>     in 16 FP registers mode.
> I allude to earlier.  Or does this restriction apply to all COP1X insns?
> (In which case I don't really understand why is singled out
> for special treatment in the documentation of madd itself.)

To answer my own question: yes.  Sorry about that.


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