Re: Clean up MIPS ISA macros

[Richard Sandiford <richard at codesourcery dot com>]

David Daney <ddaney@avtrex.com> writes:
> I think this breaks the bootstrap on mipsel-unknown-linux-gnu.  In stage 
> 2 we are building with -Werror and now have:
>
> /home/build/gcc-build/./prev-gcc/xgcc 
> -B/home/build/gcc-build/./prev-gcc/ 
> -B/usr/local/mipsel-unknown-linux-gnu/bin/ -c   -g -O2 -DIN_GCC   -W 
> -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -pedantic 
> -Wno-long-long -Wno-variadic-macros -Wno-overlength-strings 
> -Wold-style-definition -Wmissing-format-attribute -Werror -fno-common 
> -DHAVE_CONFIG_H -I. -I. -I../../gcc/gcc -I../../gcc/gcc/. 
> -I../../gcc/gcc/../include -I../../gcc/gcc/../libcpp/include 
> -I../../gcc/gcc/../libdecnumber -I../libdecnumber    insn-emit.c -o 
> insn-emit.o
> cc1: warnings being treated as errors
> ../../gcc/gcc/config/mips/mips.md: In function 'gen_muldi3':
> ../../gcc/gcc/config/mips/mips.md:1018: warning: implicit declaration of 
> function 'gen_muldi3_mult3'
> ../../gcc/gcc/config/mips/mips.md:1018: warning: passing argument 1 of 
> 'emit_insn' makes pointer from integer without a cast

Sorry once again ;(.  I've committed the patch below after verifying
that we no longer get that warning and that libgcc still builds correctly.
I'll run full tests overnight to double-check it.

Richard


gcc/
	* config/mips/mips.md (mul<mode>3): Split into...
	(mulsi3, muldi3): ...these separate patterns.

Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	(revision 118188)
+++ gcc/config/mips/mips.md	(working copy)
@@ -1008,19 +1008,31 @@ (define_insn "mulv2sf3"
 ;; These processors have PRId values of 0x00004220 and 0x00004300,
 ;; respectively.
 
-(define_expand "mul<mode>3"
-  [(set (match_operand:GPR 0 "register_operand")
-	(mult:GPR (match_operand:GPR 1 "register_operand")
-		  (match_operand:GPR 2 "register_operand")))]
+(define_expand "mulsi3"
+  [(set (match_operand:SI 0 "register_operand")
+	(mult:SI (match_operand:SI 1 "register_operand")
+		 (match_operand:SI 2 "register_operand")))]
   ""
 {
-  if (<MODE>mode == SImode && ISA_HAS_MUL3)
-    emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
-  else if (!TARGET_FIX_R4000)
-    emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
-					operands[2]));
+  if (ISA_HAS_MUL3)
+    emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
+  else if (TARGET_FIX_R4000)
+    emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
+  else
+    emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
+  DONE;
+})
+
+(define_expand "muldi3"
+  [(set (match_operand:DI 0 "register_operand")
+	(mult:DI (match_operand:DI 1 "register_operand")
+		 (match_operand:DI 2 "register_operand")))]
+  "TARGET_64BIT"
+{
+  if (TARGET_FIX_R4000)
+    emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
   else
-    emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
+    emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
   DONE;
 })