This patch cleans up the MIPS ISA macros slightly:
- GENERATE_MULT3_DI is effectively dead code. It is only true for
the tx39 (a 32-bit target), yet the only pattern that depends on it
requires TARGET_64BIT. The pattern generates a three-operand dmult,
which doesn't exist on any target I know, and is not recognised by
I assume this pattern was added in case some future 64-bit target
needed it, but the recent convention has been to call the 3-operand
instruction "mul" rather than "mult", so it seems very unlikely that
any future target will add a 3-operand dmult. The patch therefore
removes both the macro and the pattern.
- Also, because "mul" is the standard name of the 3-operand form,
we might as well use an inclusive test for "mult" rather than "mul".
It's much shorter.
- The ISA_HAS_ROTR_SI/DI pair is an odd one out. The convention is to
use the same macro for both 32-bit and 64-bit insns where possible,
and to also use TARGET_64BIT for the 64-bit forms. (The :GPR macro
adds the TARGET_64BIT check automatically.) The patch therefore
replaces this pair with ISA_HAS_ROR.
- ISA_HAS_DCLZ_DCLO was unused. The dclo and dclz patterns had
already been converted to use ISA_HAS_CLZ_CLO && TARGET_64BIT.
- Some non-MIPS16 insns were not protected by !TARGET_MIPS16.
These insns were only selected for targets that don't support
the MIPS16 ASE, but I think all non-MIPS16 insns should be
marked as such for consistency. "gcc -march=vr5400 -mips16"
might not make much sense, but it certainly shouldn't generate
a mixture of MIPS16 and normal-mode VR5400 code.
- The formatting was very inconsistent. I went for the most common
form across the board.
Tested on mips64-linux-gnu. Applied to mainline. Not a big step
forward by any means, but...
* config/mips/mips.md (mul<mode>3): Check ISA_HAS_MUL3 rather than
GENERATE_MULT3_<MODE>. Restrict the test to SImode. Use ISA_HAS_MUL3
rather than GENERATE_MULT3_SI in the various define_peephole2s.
(mulsi3_mult3): Depend on ISA_HAS_MUL3 rather than GENERATE_MULT3_SI.
Use an inclusive test for "mult" rather than "mul".
(rotr<mode>3): Depend on ISA_HAS_ROR.
* config/mips/mips.h (GENERATE_MULT3_SI): Delete in favor of
(ISA_HAS_64BIT_REGS): Use consistent formatting.
(ISA_HAS_MUL3): New macro.
(ISA_HAS_CONDMOVE, ISA_HAS_8CC): Use consistent formatting.
(ISA_HAS_FP4, ISA_HAS_MADD_MSUB, ISA_HAS_NMADD_NMSUB): Likewise.
(ISA_HAS_MULHI, ISA_HAS_MULS, ISA_HAS_MSAC): Require !TARGET_MIPS16.
(ISA_HAS_MACC): Require !TARGET_MIPS16 for all ISAs, not just
the VR4120 and VR4130.
(ISA_HAS_MACCHI): Use consistent formatting.
(ISA_HAS_ROTR_SI, ISA_HAS_ROTR_DI): Delete in favor of...
(ISA_HAS_ROR): ...this new macro.
(ISA_HAS_PREFETCH, ISA_HAS_PREFETCHX): Use consistent formatting.
(ISA_HAS_SEB_SEH, ISA_HAS_EXT_INS): Likewise.
(ISA_HAS_LOAD_DELAY): Use ISA_MIPS1.