This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[patch] fisttp and sse3


So, after all of the arguments everyone seems to agree. Here's the patch again. A bit more removal as Andrew noted and I've added a testcase.

Bootstrapped and tested on x86_64-darwin. No regressions.

OK? This could be considered a fix for a regression in nocona behavior...

-eric

2006-09-18 Eric Christopher <echristo@apple.com>

* gcc.target/i386/sse3-not-fisttp.c: New.

2006-09-18 Eric Christopher <echristo@apple.com>

	* config/i386/i386.c (x86_fisttp): Remove.
 	* config/i386/i386.h (x86_fisttp): Ditto.
	(TARGET_FISTTP): Ditto.

Index: gcc/testsuite/gcc.target/i386/sse3-not-fisttp.c
===================================================================
--- gcc/testsuite/gcc.target/i386/sse3-not-fisttp.c	(revision 0)
+++ gcc/testsuite/gcc.target/i386/sse3-not-fisttp.c	(revision 0)
@@ -0,0 +1,24 @@
+/* Test that we don't generate a fisttp instruction when -mno-sse3.  */
+/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
+/* { dg-options "-O -march=nocona -mno-sse3" } */
+/* { dg-final { scan-assembler-not "fisttp" } } */
+struct foo
+{
+ long a;
+ long b;
+};
+
+extern double c;
+
+extern unsigned long long baz (void);
+
+int
+walrus (const struct foo *input)
+{
+    unsigned long long d;
+
+    d = baz ()
+      + (unsigned long long) (((double) input->a * 1000000000
+			      + (double) input->b) * c);
+    return (d ? 1 : 0);
+}
Index: gcc/config/i386/i386.h
===================================================================
--- gcc/config/i386/i386.h	(revision 117048)
+++ gcc/config/i386/i386.h	(working copy)
@@ -142,7 +142,7 @@ extern const struct processor_costs *ix8
 
 #define TUNEMASK (1 << ix86_tune)
 extern const int x86_use_leave, x86_push_memory, x86_zero_extend_with_and;
-extern const int x86_use_bit_test, x86_cmove, x86_fisttp, x86_deep_branch;
+extern const int x86_use_bit_test, x86_cmove, x86_deep_branch;
 extern const int x86_branch_hints, x86_unroll_strlen;
 extern const int x86_double_with_add, x86_partial_reg_stall, x86_movx;
 extern const int x86_use_himode_fiop, x86_use_simode_fiop;
@@ -175,8 +175,7 @@ extern int x86_prefetch_sse;
 /* For sane SSE instruction set generation we need fcomi instruction.  It is
    safe to enable all CMOVE instructions.  */
 #define TARGET_CMOVE ((x86_cmove & (1 << ix86_arch)) || TARGET_SSE)
-#define TARGET_FISTTP (((x86_fisttp & (1 << ix86_arch)) || TARGET_SSE3) \
-			&& TARGET_80387)
+#define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387)
 #define TARGET_DEEP_BRANCH_PREDICTION (x86_deep_branch & TUNEMASK)
 #define TARGET_BRANCH_PREDICTION_HINTS (x86_branch_hints & TUNEMASK)
 #define TARGET_DOUBLE_WITH_ADD (x86_double_with_add & TUNEMASK)
Index: gcc/config/i386/i386.c
===================================================================
--- gcc/config/i386/i386.c	(revision 117048)
+++ gcc/config/i386/i386.c	(working copy)
@@ -743,7 +743,6 @@ const int x86_double_with_add = ~m_386;
 const int x86_use_bit_test = m_386;
 const int x86_unroll_strlen = m_486 | m_PENT | m_PPRO | m_ATHLON_K8 | m_K6 | m_GENERIC;
 const int x86_cmove = m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
-const int x86_fisttp = m_NOCONA;
 const int x86_3dnow_a = m_ATHLON_K8;
 const int x86_deep_branch = m_PPRO | m_K6 | m_ATHLON_K8 | m_PENT4 | m_NOCONA | m_GENERIC;
 /* Branch hints were put in P4 based on simulation result. But

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]