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[m32c]Problem in bit instructions generation
- From: "Naveen H.S." <naveenh at KPITCummins dot com>
- To: <gcc-patches at gcc dot gnu dot org>
- Date: Mon, 10 Jul 2006 14:45:32 +0530
- Subject: [m32c]Problem in bit instructions generation
Hi,
I am trying to implement bit instructions for M32C target.
Even though the instructions are correctly implemented, they are
not getting generated by the compiler.
Bit instruction "btst" is not generated directly.
The implementation of "btst" instruction is as shown below.
(define_insn "btst"
[(set (reg:HI FLG_REGNO)
(zero_extract:HI (match_operand:QI 0 "mra_operand" "")
(const_int 1)
(match_operand 1 "const_int_operand" "")))]
"TARGET_A24"
"btst\t%c1,%h0"
[(set_attr "flags" "n")]
)
So I used "extzv" format to generate "btst" instruction.
In define_expand "extzv" format, I have used a function
"m32c_expand_extzv (operands)". This function is expanded in
m32c.c file, where the "btst" instruction is called using
"emit_insn" as shown below.
emit_insn (gen_btst (operands[1],operands[3]));
After this, the "btst" instruction is generated properly.
I have also implemented the other bit instructions like "band",
"bor", "bxor" and bm<cnd> etc.
Even these instructions are not getting generated directly.
Can anyone please suggest me whether there are any specific methods
to be followed to generate the bit instructions directly. Is there
any other standard formats like "extzv" other then "insv" and "extv"
that can be used for bit to bit transfer.
Regards,
Naveen.H.S.
KPIT Cummins Infosystems Ltd,
Pune (INDIA)
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