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[m32c] Implementation and enhancements of mul and div instructions
- From: "Naveen H.S." <naveenh at KPITCummins dot com>
- To: <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 5 Jul 2006 13:02:17 +0530
- Subject: [m32c] Implementation and enhancements of mul and div instructions
Hi,
Multiplication and division of 32 bit values for M32C target is done
using Library subroutines. The following patch allows for the direct
multiplication and division of 32 bit values for M32C using "mul.l",
"div.l" and "divu.l" instructions.
It also enhances the 8 bit and 16 bit multiplication instructions.
8 bit and 16 bit immediate multiplications are done directly instead
of passing the values to registers before multiplication.
Please find attached the patch below which implements the above
functionalities.
No new regressions found.
ChangeLog
2006-07-05 Naveen.H.S <naveenh@kpitcummins.com>
* config/m32c/muldiv.md (mulqihi3): Handle immediate
values directly.
(umulqihi3): Likewise.
(mulhisi3): Likewise.
(umulhisi3): Likewise.
(mulqihi3_c): Limit the mode of the 2 operand to QI
mode.
(umulqihi3_c): Limit the mode of the 2 operand to QI
mode.
(mulhisi3_c): Limit the mode of the 2 operand to HI
mode.
(umulhisi3_c): Limit the mode of the 2 operand to HI
mode.
(mulsi3): New.
(mulsi3_r): New.
(divsi3_n): New.
(divsi3): New.
(udivsi3_n): New.
(udivsi3): New.
Index: config/m32c/muldiv.md
===================================================================
--- gcc/config/m32c/muldiv.md.orig 2006-07-04 17:59:56.000000000
+0530
+++ gcc/config/m32c/muldiv.md 2006-07-05 11:49:25.000000000 +0530
@@ -26,7 +26,7 @@
(define_insn "mulqihi3_c"
[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
(mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand"
"%0,0"))
- (match_operand 2 "immediate_operand" "i,i")))]
+ (match_operand:QI 2 "immediate_operand" "i,i")))]
""
"mul.b\t%2,%1"
[(set_attr "flags" "o")]
@@ -46,7 +46,7 @@
(define_expand "mulqihi3"
[(set (match_operand:HI 0 "mra_operand"
"=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
(mult:HI (sign_extend:HI (match_operand:QI 1 "mra_operand"
"%0,0,0,0,0,0"))
- (match_operand:QI 2 "mra_operand"
"RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
+ (match_operand:QI 2 "mrai_operand"
"RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
""
"{ if (GET_MODE (operands[2]) != VOIDmode)
operands[2] = gen_rtx_SIGN_EXTEND (HImode, operands[2]); }"
@@ -55,7 +55,7 @@
(define_insn "umulqihi3_c"
[(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm")
(mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand"
"%0,0"))
- (match_operand 2 "immediate_operand" "i,i")))]
+ (match_operand:QI 2 "immediate_operand" "i,i")))]
""
"mulu.b\t%U2,%1"
[(set_attr "flags" "o")]
@@ -73,7 +73,7 @@
(define_expand "umulqihi3"
[(set (match_operand:HI 0 "mra_operand"
"=RhiSd,RhiSd,??Rmm,??Rmm,Raa,Raa")
(mult:HI (zero_extend:HI (match_operand:QI 1 "mra_operand"
"%0,0,0,0,0,0"))
- (match_operand:QI 2 "mra_operand"
"RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
+ (match_operand:QI 2 "mrai_operand"
"RqiSd,?Rmm,RqiSd,?Rmm,RhlSd,?Rmm")))]
""
"{ if (GET_MODE (operands[2]) != VOIDmode)
operands[2] = gen_rtx_ZERO_EXTEND (HImode, operands[2]); }"
@@ -82,7 +82,7 @@
(define_insn "mulhisi3_c"
[(set (match_operand:SI 0 "ra_operand" "=Rsi")
(mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand"
"%0"))
- (match_operand 2 "immediate_operand" "i")))]
+ (match_operand:HI 2 "immediate_operand" "i")))]
""
"mul.w\t%2,%1"
[(set_attr "flags" "o")]
@@ -100,7 +100,7 @@
(define_expand "mulhisi3"
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
(mult:SI (sign_extend:SI (match_operand:HI 1 "mra_operand"
"%0,0,0,0"))
- (match_operand:HI 2 "mra_operand"
"RhiSd,?Rmm,RhiSd,?Rmm")))]
+ (match_operand:HI 2 "mrai_operand"
"RhiSd,?Rmm,RhiSd,?Rmm")))]
""
"{ if (GET_MODE (operands[2]) != VOIDmode)
operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
@@ -109,7 +109,7 @@
(define_insn "umulhisi3_c"
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm")
(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand"
"%0,0"))
- (match_operand 2 "immediate_operand" "i,i")))]
+ (match_operand:HI 2 "immediate_operand" "i,i")))]
""
"mulu.w\t%u2,%1"
[(set_attr "flags" "o")]
@@ -127,7 +127,7 @@
(define_expand "umulhisi3"
[(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm")
(mult:SI (zero_extend:SI (match_operand:HI 1 "mra_operand"
"%0,0,0,0"))
- (match_operand:HI 2 "mra_operand"
"RhiSd,?Rmm,RhiSd,?Rmm")))]
+ (match_operand:HI 2 "mrai_operand"
"RhiSd,?Rmm,RhiSd,?Rmm")))]
""
"{ if (GET_MODE (operands[2]) != VOIDmode)
operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
@@ -159,6 +159,24 @@
}"
)
+(define_insn "mulsi3_r"
+ [(set (match_operand:SI 0 "m32c_hl_operand" "=R02,R02")
+ (mult:SI (match_operand:SI 1 "m32c_hl_operand" "%0,0")
+ (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
+ "TARGET_M32C"
+ "mul.l\t%2,%1"
+ [(set_attr "flags" "o")]
+ )
+
+(define_expand "mulsi3"
+ [(set (match_operand:SI 0 "m32c_hl_operand" "=R02,R02")
+ (mult:SI (match_operand:SI 1 "m32c_hl_operand" "%0,0")
+ (match_operand:SI 2 "mra_operand" "RsiSd,?Rmm")))]
+ "TARGET_M32C"
+ "{
+if ((GET_MODE (operands[2]) != SImode) && (GET_MODE (operands[2]) !=
VOIDmode))
+ operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
+)
(define_expand "divmodqi4"
@@ -260,3 +278,42 @@
"divu.w\t%2"
[(set_attr "flags" "o")]
)
+
+(define_insn "divsi3_n"
+ [(set (match_operand:SI 0 "m32c_hl_operand" "=R02,R02")
+ (div:SI (match_operand:SI 1 "m32c_hl_operand" "R02,R02")
+ (match_operand:SI 2 "general_operand" "RsiSd,?Rmm")))]
+ "TARGET_M32C"
+ "div.l\t%2"
+ [(set_attr "flags" "o")]
+)
+
+(define_expand "divsi3"
+ [(set (match_operand:SI 0 "m32c_hl_operand" "=R02,R02")
+ (div:SI (match_operand:SI 1 "m32c_hl_operand" "R02,R02")
+ (match_operand:SI 2 "general_operand" "RsiSd,?Rmm")))]
+ "TARGET_M32C"
+ "{
+ if ((GET_MODE (operands[2]) != SImode) && (GET_MODE (operands[2])
!= VOIDmode))
+ operands[2] = gen_rtx_SIGN_EXTEND (SImode, operands[2]); }"
+)
+
+(define_insn "udivsi3_n"
+ [(set (match_operand:SI 0 "m32c_hl_operand" "=R02,R02")
+ (udiv:SI (match_operand:SI 1 "m32c_hl_operand" "R02,R02")
+ (match_operand:SI 2 "general_operand" "RsiSd,?Rmm")))]
+ "TARGET_M32C"
+ "divu.l\t%2"
+ [(set_attr "flags" "o")]
+ )
+
+(define_expand "udivsi3"
+ [(set (match_operand:SI 0 "m32c_hl_operand" "=R02,R02")
+ (udiv:SI (match_operand:SI 1 "m32c_hl_operand" "R02,R02")
+ (match_operand:SI 2 "general_operand"
"RsiSd,?Rmm")))]
+ "TARGET_M32C"
+ "{
+ if ((GET_MODE (operands[2]) != SImode) && (GET_MODE (operands[2])
!= VOIDmode))
+ operands[2] = gen_rtx_ZERO_EXTEND (SImode, operands[2]); }"
+)
+
Regards,
Naveen.H.S.
KPIT Cummins Infosystems Ltd,
Pune (INDIA)
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