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[PATCH, H8/300]: Peephole for generating BSET and BCLR instructions in H8/300 target
- From: "Naveen H.S." <naveenh at KPITCummins dot com>
- To: <gcc-patches at gcc dot gnu dot org>
- Date: Tue, 14 Feb 2006 18:10:32 +0530
- Subject: [PATCH, H8/300]: Peephole for generating BSET and BCLR instructions in H8/300 target
Hi,
Please find the patch as below for H8/300 (ELF) targets H8300, H8S for
both normal and advanced modes. This patch enhances the code by
introducing two important bit instructions i.e. "BSET" and "BCLR" which
are not generated directly in GCC 4.2 for the above mentioned H8
targets; instead four separate instructions are generated to implement
the above mentioned instructions respectively.
These instructions will be generated after applying this patch by
passing any optimization option (O1 onwards) on the command line. This
can be extremely useful in the codes which are dealing with bit
instructions as it reduces the code size and hence increases the
efficiency.
No new regressions found.
=======================Start of Patch================================
ChangeLog
2006-02-14 Naveen.H.S <naveenh@kpitcummins.com>
* gcc/config/h8300/h8300.md: Peephole is added to generate
BCLR and BSET.
* gcc/config/h8300/h8300.c: New functions are defined.
* gcc/config/h8300/h8300-proros.h:New functions
declared.
--- gcc-4.2-20060204/gcc/config/h8300/h8300.md 2006-01-02
22:58:54.000000000 +0530
+++ gcc-4.2-20060204/gcc/config/h8300/h8300.md 2006-02-14
10:43:15.000000000 +0530
@@ -4428,6 +4428,56 @@
;; PEEPHOLE PATTERNS
;; -----------------------------------------------------------------
+(define_peephole
+ [(set (match_operand 0 "register_operand" "")
+ (match_operand 1 "const_int_operand" ""))
+ (set (match_operand:QI 2 "register_operand" "")
+ (match_operand:QI 3 "memory_operand" ""))
+ (set (match_dup 2)
+ (and (match_dup 2)
+ (match_operand 4 "const_int_operand" "")))
+ (set (match_dup 3)(match_dup 2))]
+ "((TARGET_H8300 || TARGET_H8300H || TARGET_H8300S)
+ && (REGNO (operands[0]) != REGNO (operands[2]))
+ &&(INTVAL(operands[4]) == -2||INTVAL(operands[4]) == -3
+ ||INTVAL(operands[4]) == -5 ||INTVAL(operands[4]) == -9
+ ||INTVAL(operands[4]) == -17||INTVAL(operands[4]) == -33
+ ||INTVAL(operands[4]) == -65||INTVAL(operands[4]) == 127))"
+
+ "*
+ {
+ if (TARGET_H8300S && !TARGET_NORMAL_MODE)
+ return op_bit_clear_h8s(operands);
+ else
+ return op_bit_clear(operands);
+ }"
+)
+
+(define_peephole
+ [(set (match_operand 0 "register_operand" "")
+ (match_operand 1 "const_int_operand" ""))
+ (set (match_operand:QI 2 "register_operand" "")
+ (match_operand:QI 3 "memory_operand" ""))
+ (set (match_dup 2)
+ (ior (match_dup 2)
+ (match_operand 4 "const_int_operand" "")))
+ (set (match_dup 3)(match_dup 2))]
+ "((TARGET_H8300 || TARGET_H8300H || TARGET_H8300S)
+ && (REGNO (operands[0]) != REGNO (operands[2]))
+ &&(INTVAL(operands[4]) == 1||INTVAL(operands[4]) == 2
+ ||INTVAL(operands[4]) == 4 ||INTVAL(operands[4]) == 8
+ ||INTVAL(operands[4]) == 16||INTVAL(operands[4]) == 32
+ ||INTVAL(operands[4]) == 64||INTVAL(operands[4]) == -128))"
+
+ "*
+ {
+ if (TARGET_H8300S && !TARGET_NORMAL_MODE)
+ return op_bit_set_h8s(operands);
+ else
+ return op_bit_set(operands);
+ }"
+)
+
;; Convert (A >> B) & C to (A & 255) >> B if C == 255 >> B.
(define_peephole2
--- gcc-4.2-20060204/gcc/config/h8300/h8300.c 2005-06-25
06:52:41.000000000 +0530
+++ gcc-4.2-20060204/gcc/config/h8300/h8300.c 2006-02-12
18:57:14.000000000 +0530
@@ -2392,7 +2392,6 @@ h8300_mova_length (rtx dest, rtx src, rt
size += 2;
return size;
}
-
/* Compute the length of INSN based on its length_table attribute.
OPERANDS is the array of its operands. */
@@ -2451,6 +2450,101 @@ h8300_insn_length_from_table (rtx insn,
}
}
+/* Return the asm template for h8 bitset instruction */
+const char *
+op_bit_set(rtx * operands)
+{
+ switch(INTVAL(operands[4]))
+ {
+ case 1: return "bset #0,@%o1:8";
+ break;
+ case 2: return "bset #1,@%o1:8";
+ break;
+ case 4: return "bset #2,@%o1:8";
+ break;
+ case 8: return "bset #3,@%o1:8";
+ break;
+ case 16:return "bset #4,@%o1:8";
+ break;
+ case 32:return "bset #5,@%o1:8";
+ break;
+ case 64:return "bset #6,@%o1:8";
+ break;
+ case -128:return "bset #7,@%o1:8";
+ break;
+ }
+}
+
+/* Return the asm template for h8s bitset instruction */
+const char *
+op_bit_set_h8s(rtx * operands)
+{
+ switch(INTVAL(operands[4]))
+ {
+ case 1: return "bset #0,@%o1";
+ break;
+ case 2: return "bset #1,@%o1";
+ break;
+ case 4: return "bset #2,@%o1";
+ break;
+ case 8: return "bset #3,@%o1";
+ break;
+ case 16:return "bset #4,@%o1";
+ break;
+ case 32:return "bset #5,@%o1";
+ break;
+ case 64:return "bset #6,@%o1";
+ break;
+ case -128:return "bset #7,@%o1";
+ break;
+ }
+}
+/* Return the asm template for h8s bitclear instruction */
+const char *
+op_bit_clear_h8s(rtx * operands)
+{
+ switch(INTVAL(operands[4]))
+ {
+ case -2: return "bclr #0,@%o1";
+ break;
+ case -3: return "bclr #1,@%o1";
+ break;
+ case -5: return "bclr #2,@%o1";
+ break;
+ case -9: return "bclr #3,@%o1";
+ break;
+ case -17:return "bclr #4,@%o1";
+ break;
+ case -33:return "bclr #5,@%o1";
+ break;
+ case -65:return "bclr #6,@%o1";
+ break;
+ case 127:return "bclr #7,@%o1";
+ break;
+ }
+}
+ /* Return the asm template for h8 bitclear instruction */
+const char *
+op_bit_clear(rtx * operands)
+{
+ switch(INTVAL(operands[4]))
+ {
+ case -2: return "bclr #0,@%o1:8";
+ break;
+ case -3: return "bclr #1,@%o1:8";
+ break;
+ case -5: return "bclr #2,@%o1:8";
+ break;
+ case -9: return "bclr #3,@%o1:8";
+ break;
+ case -17:return "bclr #4,@%o1:8";
+ break;
+ case -33:return "bclr #5,@%o1:8";
+ break;
+ case -65:return "bclr #6,@%o1:8";
+ break;
+ case 127:return "bclr #7,@%o1:8";
+ break;
+ }
+}
/* Return true if LHS and RHS are memory references that can be mapped
to the same h8sx assembly operand. LHS appears as the destination
of
an instruction and RHS appears as a source.
--- gcc-4.2-20060204/gcc/config/h8300/h8300-protos.h 2005-06-25
06:52:41.000000000 +0530
+++ gcc-4.2-20060204/gcc/config/h8300/h8300-protos.h 2006-02-12
01:19:13.000000000 +0530
@@ -52,6 +52,10 @@ extern int expand_a_rotate (rtx[]);
extern int fix_bit_operand (rtx *, enum rtx_code);
extern int h8300_adjust_insn_length (rtx, int);
extern void split_adds_subs (enum machine_mode, rtx[]);
+extern const char * op_bit_clear_h8s(rtx * operands);
+extern const char * op_bit_clear(rtx * operands);
+extern const char * op_bit_set_h8s(rtx * operands);
+extern const char * op_bit_set(rtx * operands);
extern int h8300_eightbit_constant_address_p (rtx);
extern int h8300_tiny_constant_address_p (rtx);
=======================End Of Patch================================
Regards,
Naveen.H.S.
KPIT Cummins Infosystems Ltd,
Pune ( INDIA )
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