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[patch] gcc/*: Fix comment typos. Follow spelling conventions.


Hi,

Committed as obvious.  Daniel Berlin asked me to check in the
tree-vect-transform.c bits.

Kazu Hirata

2005-09-30  Kazu Hirata  <kazu@codesourcery.com>

	* tree-vect-transform.c, config/ms1/ms1.md,
	config/s390/s390.c, config/v850/v850.md: Fix comment typos.
	Follow spelling conventions.
	* doc/invoke.texi, doc/md.texi: Fix typos.

Index: tree-vect-transform.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/tree-vect-transform.c,v
retrieving revision 2.45
diff -u -d -p -r2.45 tree-vect-transform.c
--- tree-vect-transform.c	19 Sep 2005 09:02:23 -0000	2.45
+++ tree-vect-transform.c	30 Sep 2005 15:24:02 -0000
@@ -1781,7 +1781,7 @@ vectorizable_load (tree stmt, block_stmt
 	     the value of the parameter and no global variables are touched
 	     which makes the builtin a "const" function.  Requiring the
 	     builtin to have the "const" attribute makes it unnecessary
-	     to call mark_call_clobbered_vars_to_rename.  */
+	     to call mark_call_clobbered.  */
 	  gcc_assert (TREE_READONLY (builtin_decl));
 	}
       else
Index: config/ms1/ms1.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ms1/ms1.md,v
retrieving revision 1.2
diff -u -d -p -r1.2 ms1.md
--- config/ms1/ms1.md	6 Sep 2005 02:04:57 -0000	1.2
+++ config/ms1/ms1.md	30 Sep 2005 15:24:03 -0000
@@ -243,7 +243,7 @@
 	DONE;
     }
 
-   /* If the load is a psuedo register in a stack slot, some simplification
+   /* If the load is a pseudo register in a stack slot, some simplification
       can be made because the loads are aligned */
   if ( (! TARGET_BYTE_ACCESS) 
         && (reload_in_progress && GET_CODE (operands[1]) == SUBREG
@@ -417,7 +417,7 @@
 	DONE;
     }
 
-   /* If the load is a psuedo register in a stack slot, some simplification
+   /* If the load is a pseudo register in a stack slot, some simplification
       can be made because the loads are aligned */
   if ( (reload_in_progress && GET_CODE (operands[1]) == SUBREG
 	  && GET_CODE (SUBREG_REG (operands[1])) == REG
Index: config/s390/s390.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/s390/s390.c,v
retrieving revision 1.256
diff -u -d -p -r1.256 s390.c
--- config/s390/s390.c	16 Sep 2005 14:25:20 -0000	1.256
+++ config/s390/s390.c	30 Sep 2005 15:24:03 -0000
@@ -1099,7 +1099,7 @@ s390_overlap_p (rtx mem1, rtx mem2, HOST
      Overlapping operations would otherwise be recognized by the S/390 hardware
      and would fall back to a slower implementation. Allowing overlapping 
      operations would lead to slow code but not to wrong code. Therefore we are
-     somewhat optimistict if we cannot prove that the memory blocks are 
+     somewhat optimistic if we cannot prove that the memory blocks are 
      overlapping.
      That's why we return false here although this may accept operations on
      overlapping memory areas.  */
Index: config/v850/v850.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/v850/v850.md,v
retrieving revision 1.36
diff -u -d -p -r1.36 v850.md
--- config/v850/v850.md	28 Sep 2005 15:56:53 -0000	1.36
+++ config/v850/v850.md	30 Sep 2005 15:24:04 -0000
@@ -1309,7 +1309,7 @@
   /* Branch to the default label if out of range of the table.  */
   emit_jump_insn (gen_bgtu (operands[4]));
 
-  /* Disabled because the switch pattern is not being recognised
+  /* Disabled because the switch pattern is not being recognized
      properly at the moment.  eg. compiling vfscanf.c in newlib.  */
   if (0 && ! TARGET_BIG_SWITCH && TARGET_V850E)
     {
Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.679
diff -u -d -p -r1.679 invoke.texi
--- doc/invoke.texi	27 Sep 2005 03:11:28 -0000	1.679
+++ doc/invoke.texi	30 Sep 2005 15:24:04 -0000
@@ -5912,7 +5912,7 @@ Bound on size of expressions used in the
 Large expressions slow the analyzer.
 
 @item vect-max-version-checks
-The maxinum number of runtime checks that can be performed when doing
+The maximum number of runtime checks that can be performed when doing
 loop versioning in the vectorizer.  See option ftree-vect-loop-version
 for more information.
 
Index: doc/md.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/md.texi,v
retrieving revision 1.146
diff -u -d -p -r1.146 md.texi
--- doc/md.texi	22 Aug 2005 16:12:13 -0000	1.146
+++ doc/md.texi	30 Sep 2005 15:24:04 -0000
@@ -3086,14 +3086,14 @@ modes.
 
 @cindex @code{reduc_splus_@var{m}} instruction pattern
 @item @samp{reduc_splus_@var{m}}
-Compute the sum of the signed elements of a vector. The vector is opernad 1, 
-and the scalar result is stored in the least significant bits of opernad 0 
+Compute the sum of the signed elements of a vector. The vector is operand 1, 
+and the scalar result is stored in the least significant bits of operand 0 
 (also a vector). The output and input vector should have the same modes.
 
 @cindex @code{reduc_uplus_@var{m}} instruction pattern
 @item @samp{reduc_uplus_@var{m}}
-Compute the sum of the unsigned elements of a vector. The vector is opernad 1, 
-and the scalar result is stored in the least significant bits of opernad 0 
+Compute the sum of the unsigned elements of a vector. The vector is operand 1, 
+and the scalar result is stored in the least significant bits of operand 0 
 (also a vector). The output and input vector should have the same modes.
 
 @cindex @code{vec_shl_@var{m}} instruction pattern


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