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Re: [patch RFC] SH: PR target/21623


> It sounds fine, though I can't understand how to split insns
> between the reload and the postreload passes.  The post-reload
> split pass runs after postreload where the ICE happens.

Oops, I misunderstood.  I should read your suggestion more carefully.
I'm now testing the appended patch.

Regards,
	kaz
--
	* config/sh/sh.md (movsi_ie): Add case for moving from T
	register to a FP register.
	(movsi_ie splitter): New.
	(fldi0, cmovsf1): New insn. 

--- ORIG/gcc/gcc/config/sh/sh.md	2005-09-14 08:08:20.000000000 +0900
+++ TMP/gcc/gcc/config/sh/sh.md	2005-09-27 15:51:03.000000000 +0900
@@ -4772,9 +4772,9 @@ label:
 ;; TARGET_FMOVD is in effect, and mode switching is done before reload.
 (define_insn "movsi_ie"
   [(set (match_operand:SI 0 "general_movdst_operand"
-	    "=r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,y")
+	    "=r,r,r,t,r,r,r,r,m,<,<,x,l,x,l,y,<,r,y,r,*f,y,*f,f,y")
 	(match_operand:SI 1 "general_movsrc_operand"
-	 "Q,rI08,I20,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,y"))]
+	 "Q,rI08,I20,r,mr,x,l,t,r,x,l,r,r,>,>,>,y,i,r,y,y,*f,*f,t,y"))]
   "(TARGET_SH2E || TARGET_SH2A)
    && (register_operand (operands[0], SImode)
        || register_operand (operands[1], SImode))"
@@ -4802,10 +4802,11 @@ label:
 	fsts	fpul,%0
 	flds	%1,fpul
 	fmov	%1,%0
+	bf/s 0f\;fldi0 %0\;fldi1 %0\\n0:
 	! move optimized away"
-  [(set_attr "type" "pcload_si,move,move,*,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,nil")
-   (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*")
-   (set_attr "length" "*,*,4,*,4,*,*,*,4,*,*,*,*,*,*,*,*,*,*,*,*,*,*,0")])
+  [(set_attr "type" "pcload_si,move,move,*,load_si,mac_gp,prget,move,store,store,pstore,move,prset,load,pload,load,store,pcload_si,gp_fpul,fpul_gp,fmove,fmove,fmove,fmove,nil")
+   (set_attr "late_fp_use" "*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,*,yes,*,*,yes,*,*,*,*,*")
+   (set_attr "length" "*,*,4,*,4,*,*,*,4,*,*,*,*,*,*,*,*,*,*,*,*,*,*,6,0")])
 
 (define_insn "movsi_i_lowpart"
   [(set (strict_low_part (match_operand:SI 0 "general_movdst_operand" "+r,r,r,r,r,r,m,r"))
@@ -6574,6 +6575,37 @@ label:
   "TARGET_SH1"
   [(set (match_dup 0) (match_dup 1))]
   "")
+
+;; Post-reload split to give more scheduling freedom when moving T
+;; register to a FP register.
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "")
+	(reg:SI T_REG))]
+  "TARGET_HARD_SH4 && reload_completed
+   && FP_REGISTER_P (true_regnum (operands[0]))"
+  [(const_int 0)]
+  "emit_insn (gen_fldi0 (operands[0], get_fpscr_rtx ()));
+   emit_insn (gen_cmovsf1 (operands[0], operands[0]));
+   DONE;")
+
+(define_insn "fldi0"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(const_int 0))
+   (use (match_operand:PSI 1 "fpscr_operand" "c"))]
+  "TARGET_SH2E"
+  "fldi0 %0"
+  [(set_attr "type" "fmove")
+   (set_attr "length" "2")])
+
+(define_insn "cmovsf1"
+  [(set (match_operand:SI 0 "register_operand" "=f")
+	(if_then_else:SI (eq:SI (reg:SI T_REG) (const_int 0))
+		      (match_operand:SI 1 "arith_reg_operand" "0")
+		      (const_int 1)))]
+  "TARGET_HARD_SH4"
+  "bf 0f\;fldi1 %0\\n0:"
+  [(set_attr "type" "arith")
+   (set_attr "length" "4")])
 
 ;; ------------------------------------------------------------------------
 ;; Define the real conditional branch instructions.


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