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Re: patch [RFC] one's complement of vector floats ICE for x86 targets.



On Sep 13, 2005, at 12:39 PM, Richard Henderson wrote:


On Mon, Sep 12, 2005 at 09:55:13AM -0700, Fariborz Jahanian wrote:

gcc ICEs on one's complement of vector floats for all x86 targets
with -O1 (or more) and -msse.


This should be denied in the front-end, since it doesn't make sense. One can't apply the bit-negation operator to scalar floats either,

Yes. Scalar codes are rejected as they should. However, complement of vector floats have been accepted by 3.3 onward and we have users which rely on them. BTW, altivec PIM defines vec_xor on two vector floats and returns a vector float, even though scalar version is also disallowed. So it seems that in the land of vector operations, such idiotic conversions are sometimes allowed. Is there a workaround that I can pass to the user (c++'s reinterpre_cast of elements come to mind).


- fariborz

after all.


r~




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