Re: [patch] Fix behavior of TER on unrolled loops

[kenner at vlsi1 dot ultra dot nyu dot edu (Richard Kenner)]

    Zdenek> I find it more senseful to make a simple pass (SR) more clever,
    Zdenek> than making the task that is already almost impossible to solve
    Zdenek> as it is (RA) more complex.

    SR occurs too early to have an accurate model of register pressure
    and to infer the final instructions that will be produced.  Tuning and
    maintaining the heuristics and the register pressure information for every
    future change to GCC's optimization information is an unnecessary and
    unproductive burden.

    The consensus among GCC developers is toward light-weight,
    narrowly-defined optimization passes, including later passes to
    reconstitute loops or complicated addressing modes to match target
    dependencies based upon more accurate information.

    You seem to have a different mental model of the optimization
    design for GCC than most other GCC developers.  The fundamental
    disagreement is that you have a different premise than most other GCC
    developers and with the way that GCC development is headed.  

I don't think that's fair.  Certainly everybody is in favor of doing things
as simply as possible, but the world doesn't always cooperate in that effort!

I agree with Zdenek that it's critical that SR knows about addressing modes
because a large portion of givs are inside addressing mode calculations.
Knowing what addressing modes are available is critical in knowing which to
reduce and how to express one giv as a form of another.  I think the current
RTL optimizer does too *little* of this, not too much.  Indeed, quite a
number of years ago, I started a (now abandoned) project to increase this
knowlege and it helped noticably.  One would expect a more modern effort
taking advantage of the more available global information to be even better.

I disagree with the view that because we have enough (over 30) registers, we
don't have to worry about pressure caused by an overly-agressive SR.  For
example, consider nested loops whether the outer loop needs a moderate number
of registers itself.

There are quite a number of ways to have SR know about this information.
We can defer it to the RTL level, canonicalize addressing at the tree level
and have a way for it to ask which addressing modes are valid (in a similar
way to how the RTL pass would do it), or any number of other schemes.  But
my feeling is that some such is needed.