This is the mail archive of the mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: [PATCH] MIPS32 DSP intrinsics

  Here is the latest MIPS32 DSP ASE patch.  Major changes from the last

1. Add DSP_ACC_REGS class for 6 new DSP accumulators only.
2. Enable a move pattern from 6 new DSP accumulators to integer registers.
3. Restore original code of mfhilo_<mode>, because only HI/LO ($ac0) has the
4. Add two tests: mips32-dsp.c mips32-dsp-type.c for scanning
assembly instructions.  (I also tested by executing them using our

# make RUNTEST=/home/dejagnu/runtest check-gcc
RUNTESTFLAGS="--target_board=mips-sim  mips.exp=mips32-dsp*"

                === gcc Summary ===

# of expected passes            97
/home/sweng_scratrch1/gcc-mainline/builddsp/gcc/xgcc  version 4.1.0 20050712

  I didn't bootstrap GCC, but just checked the warning message while
building GCC..


2005-07-12  Chao-ying Fu  <>

    * config/mips/ New file.
    * config/mips/mips-modes.def (V4QI, V2HI, CCDSP): New modes.
    * config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Add __mips_dsp.
    (ASM_SPEC): Map -mdsp to -mdsp in GAS.
    (FIRST_PSEUDO_REGISTER): Increase to 188 because of 6 DSP accumulators
    and 6 DSP control registers.
    Update for 12 new DSP registers.
    New define.
    (DSP_ACC_REG_P, ACC_REG_P, ACC_HI_REG_P): New define.
    (reg_class): Add DSP_ACC_REGS and ACC_REGS.
    (REG_CLASS_NAMES): Add names for DSP_ACC_REGS and ACC_REGS.
    (REG_ALLOC_ORDER): Update for 12 new DSP registers.
    (mips_char_to_class): Add 'A' for DSP_ACC_REGS and 'a' for ACC_REGS.
    (UIMM6_OPERAND, IMM10_OPERAND): New define.
    (YA, YB): New extra two-letter constraints.
    (EXTRA_CONSTRAINT_Y): Add YA and YB extra constraints.
    (REGISTER_NAMES): Add names for 12 new DSP registers.
    * config/mips/mips.c (mips_function_type): Add types for DSP builtin
    (mips_builtin_type): Add MIPS_BUILTIN_DIRECT_NO_TARGET and
    (mips_expand_builtin_direct): Add one parameter to indicate that
    builtin functions need to return a value.
    (mips_expand_builtin_bposge): New for expanding "bposge" builtin
    (mips_regno_to_class): Add classes for 12 new DSP registers.
    (mips_subword): Change to check four HI registers.
    (mips_output_move): Output move to and from 6 new DSP accumulators.
    (override_options): Make sure -mdsp and -mips16 are not used together.
    Map 'A' to DSP_ACC_REGS and 'a' to ACC_REGS.  Enable DSP accumulators
    for machine modes.
    (mips_conditional_register_usage): Disable 6 new DSP accumulators
    when !TARGET_DSP.
    (print_operand): Add 'q' for printing DSP accumulators.
    (mips_cannot_change_mode_class): Check ACC_REGS.
    (mips_secondary_reload_class): Check ACC_REGS.
    (mips_vector_mode_supported_p): Enable V2HI and V4QI when TARGET_DSP.
    (mips_register_move_cost): Check ACC_REGS.
    (CODE_FOR_mips_addq_ph, CODE_FOR_mips_addq_s_ph, CODE_FOR_mips_addq_s_w,
    CODE_FOR_mips_addu_qb, CODE_FOR_mips_addu_s_qb, CODE_FOR_mips_subq_ph,
    CODE_FOR_mips_subq_s_ph, CODE_FOR_mips_subq_s_w, CODE_FOR_mips_subu_qb,
    CODE_FOR_mips_subu_s_qb, CODE_FOR_mips_absq_s_ph,
    CODE_FOR_mips_absq_s_w, CODE_FOR_mips_shll_qb, CODE_FOR_mips_shll_ph,
    CODE_FOR_mips_shll_s_ph, CODE_FOR_mips_shll_s_w,
    CODE_FOR_mips_shra_r_ph, CODE_FOR_mips_shra_r_w,
    CODE_FOR_mips_cmpu_eq_qb, CODE_FOR_mips_cmpu_lt_qb,
    CODE_FOR_mips_cmpu_le_qb, CODE_FOR_mips_cmp_eq_ph,
    CODE_FOR_mips_cmp_lt_ph, CODE_FOR_mips_cmp_le_ph, CODE_FOR_mips_pick_qb,
    CODE_FOR_mips_pick_ph, CODE_FOR_mips_bposge32): New define.
    (DIRECT_NO_TARGET_BUILTIN, BPOSGE_BUILTIN): New define for builtin
    (dsp_bdesc): New for DSP builtin functions.
    (bdesc_arrays): Add DSP builtin function table.
    (mips_prepare_builtin_arg): Change to check predicate again after
    (mips_expand_builtin): Add one more parameter to
    mips_expand_builtin_direct. Expand MIPS_BUILTIN_DIRECT_NO_TARGET and
    (mips_init_builtins): Initialize new function types.
    (mips_expand_builtin_direct): Check if builtin functions need to
    return a value and pass operands properly.
    (mips_expand_builtin_bposge): New for expanding "bposge" builtin
    * config/mips/ (UNSPEC_ADDQ .. UNSPEC_RDDSP): New unspec.
    (*movdi_32bit): Change 'x' to 'a' for ACC_REGS.
    (*movsi_internal): Change 'x' to 'a' for ACC_REGS.  Add one move pattern
    from 'A' to 'd'.
    ( New include.
    * config/mips/mips.opt (-mdsp): New option.
    * config/mips/ (const_uimm6_operand, const_imm10_operand,
    reg_imm10_operand): New predicates.
    * doc/invoke.texi (-mdsp): Document new option.
    * doc/extend.texi (MIPS DSP Builtin Functions): New section.
    * testsuite/ New test.
    * testsuite/ New test.

----- Original Message ----- 
From: "Chao-ying Fu" <>
To: "Richard Sandiford" <>
Cc: "Thekkath, Radhika" <>;
Sent: Tuesday, July 12, 2005 11:33 AM
Subject: Re: [PATCH] MIPS32 DSP intrinsics

>   After I talked to our architect, the restriction
> doesn't apply to $ac1, $ac2, $ac3.  So, I will
> create a new class that contains only $ac1, $ac2,
> $ac3 and allow moving between GPR and $ac1, $ac2,
> $ac3.
>   Yes, we have MIPS64 DSP ASE, but we focus on
> patching MIPS32 DSP ASE first.  Thanks!
> Regards,
> Chao-ying
> ----- Original Message ----- 
> From: "Richard Sandiford" <>
> To: "Chao-ying Fu" <>
> Cc: "Thekkath, Radhika" <>;
> <>
> Sent: Friday, July 08, 2005 12:48 PM
> Subject: Re: [PATCH] MIPS32 DSP intrinsics
> > "Chao-ying Fu" <> writes:
> > >   Previously, I didn't notice that from the MIPS ISA spec.
> > > mtlo/mthi will destroy hi/lo if they are moved between
> > > {mult, ...} and mfhi/mflo.  The same restriction applies
> > > to $ac1, $ac2, $ac3.
> >
> > Ick!  Ick!  Ick!  I was hoping a modern ISA like MIPS32r2
> > would avoid this sort of thing ;)
> >
> > > I will try to allocate 6 unused single characters for 6 new classes.
> > > Or, are there other ways to deal with this restriction?
> >
> > It depends.  Is this patch the complete DSP patch, or is there
> > more to follow (e.g. for MIPS64r2?).
> >
> > If this is the complete patch, I notice that all of the DSP operands
> > use or set the full DImode register.  You could therefore try
> > the new registers to DImode and using patterns like ldl/ldr to handle
> > moves to and from GPRs.
> >
> > > NOTE: It seems that GCC3.4 doesn't implement this restriction
> > > of mtlo/mthi in "".
> >
> > That's right.  The bug was fixed after 3.4 branched, and since it
> > wasn't a regression, it wasn't backported to release branches.
> >
> > Richard
> >

Attachment: mips-dsp.diff
Description: Binary data

Description: Binary data

Attachment: mips32-dsp.c
Description: Binary data

Attachment: mips32-dsp-type.c
Description: Binary data

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]