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PATCH RFA: Remove the MIPS integer abs pattern


The MIPS backend has implemented an integer abs pattern since it was
first checked in in 1992.  I believe the pattern was originally
written in order to take advantage of the jump delay slot, at a time
when gcc was not particularly good at doing that.  However, gcc is now
perfectly able to fill jump delay slots.  Moreover, gcc now implements
a slightly more efficient algorithm for abs anyhow, one which does not
require a jump at all.

For this test case:

int foo (int i) { return __builtin_abs (i); }

current gcc generates:

	bgez	$4,1f
	move	$2,$4
	subu	$2,$0,$2
1:
	j	$31
	nop

gcc with the simple appended patch, which removes the named pattern,
generates:

	sra	$2,$4,31
	xor	$4,$2,$4
	j	$31
	subu	$2,$4,$2

Removing the named pattern also makes it possible to fill branch delay
slots which appear immediately before the code which takes the
absolute value.  That currently can not be done.  For example, for
this test case:

int bar (int i) { return i < 10 ? __builtin_abs (i) : i; }

current gcc generates:

	slt	$2,$4,10
	beq	$2,$0,.L4
	nop

	bltzl	$4,1f
	subu	$4,$0,$4
1:
.L4:
	j	$31
	move	$2,$4

gcc with the appended patch generates:

	slt	$2,$4,10
	beq	$2,$0,.L4
	sra	$3,$4,31

	xor	$4,$4,$3
	subu	$4,$4,$3
.L4:
	j	$31
	move	$2,$4

So overall I think we generate better code by removing the special
handling of abs from the MIPS backend.

This patch has not been very seriously tested (I don't have any MIPS
hardware).  It's hard to see how it could cause any trouble.

Ian


2005-07-06  Ian Lance Taylor  <ian@airs.com>

	* config/mips/mips.md (abs<mode>2) [GPR]: Remove.


Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.324
diff -u -r1.324 mips.md
--- config/mips/mips.md	25 Jun 2005 01:21:46 -0000	1.324
+++ config/mips/mips.md	7 Jul 2005 06:23:36 -0000
@@ -1898,20 +1898,6 @@
 ;; exception on -2147483648 (sigh).
 
 (define_insn "abs<mode>2"
-  [(set (match_operand:GPR 0 "register_operand" "=d")
-	(abs:GPR (match_operand:GPR 1 "register_operand" "d")))]
-  "!TARGET_MIPS16"
-{
-  if (REGNO (operands[0]) == REGNO (operands[1]) && GENERATE_BRANCHLIKELY)
-    return "%(bltzl\t%1,1f\;<d>subu\t%0,%.,%0\n%~1:%)";
-  else
-    return "%(bgez\t%1,1f\;move\t%0,%1\;<d>subu\t%0,%.,%0\n%~1:%)";
-}
-  [(set_attr "type" "multi")
-   (set_attr "mode" "<MODE>")
-   (set_attr "length" "12")])
-
-(define_insn "abs<mode>2"
   [(set (match_operand:ANYF 0 "register_operand" "=f")
 	(abs:ANYF (match_operand:ANYF 1 "register_operand" "f")))]
   ""


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