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Fix some pattern names in bfin.md


Here I was wondering why the vectorizer didn't appear to do anything...


Bernd
	* config/bfin/bfin.md (addv2hi3, subv2hi3, sminv2hi3, smaxv2hi3,
	mulv2hi3, negv2hi2, absv2hi2): Pattern names fixed by appending the
	necessary digit.

Index: config/bfin/bfin.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/bfin/bfin.md,v
retrieving revision 1.7
diff -c -p -r1.7 bfin.md
*** config/bfin/bfin.md	25 Jun 2005 11:52:32 -0000	1.7
--- config/bfin/bfin.md	30 Jun 2005 07:42:31 -0000
***************
*** 1941,1947 ****
  
  ;;; Vector instructions
  
! (define_insn "addv2hi"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
--- 1941,1947 ----
  
  ;;; Vector instructions
  
! (define_insn "addv2hi3"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(plus:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
***************
*** 1949,1955 ****
    "%0 = %1 +|+ %2;"
    [(set_attr "type" "dsp32")])
  
! (define_insn "subv2hi"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
--- 1949,1955 ----
    "%0 = %1 +|+ %2;"
    [(set_attr "type" "dsp32")])
  
! (define_insn "subv2hi3"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(minus:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
***************
*** 1957,1963 ****
    "%0 = %1 -|- %2;"
    [(set_attr "type" "dsp32")])
  
! (define_insn "sminv2hi"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
--- 1957,1963 ----
    "%0 = %1 -|- %2;"
    [(set_attr "type" "dsp32")])
  
! (define_insn "sminv2hi3"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(smin:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
***************
*** 1965,1971 ****
    "%0 = MIN (%1, %2) (V);"
    [(set_attr "type" "dsp32")])
  
! (define_insn "smaxv2hi"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
--- 1965,1971 ----
    "%0 = MIN (%1, %2) (V);"
    [(set_attr "type" "dsp32")])
  
! (define_insn "smaxv2hi3"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(smax:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
***************
*** 1973,1979 ****
    "%0 = MAX (%1, %2) (V);"
    [(set_attr "type" "dsp32")])
  
! (define_insn "mulv2hi"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
--- 1973,1979 ----
    "%0 = MAX (%1, %2) (V);"
    [(set_attr "type" "dsp32")])
  
! (define_insn "mulv2hi3"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(mult:V2HI (match_operand:V2HI 1 "register_operand" "d")
  		   (match_operand:V2HI 2 "register_operand" "d")))]
***************
*** 1981,1994 ****
    "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS);"
    [(set_attr "type" "dsp32")])
  
! (define_insn "negv2hi"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
    ""
    "%0 = - %1 (V);"
    [(set_attr "type" "dsp32")])
  
! (define_insn "absv2hi"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
    ""
--- 1981,1994 ----
    "%h0 = %h1 * %h2, %d0 = %d1 * %d2 (IS);"
    [(set_attr "type" "dsp32")])
  
! (define_insn "negv2hi2"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(neg:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
    ""
    "%0 = - %1 (V);"
    [(set_attr "type" "dsp32")])
  
! (define_insn "absv2hi2"
    [(set (match_operand:V2HI 0 "register_operand" "=d")
  	(abs:V2HI (match_operand:V2HI 1 "register_operand" "d")))]
    ""

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